MC56F8323PB View Datasheet(PDF) - Motorola => Freescale
Part Name
Description
Manufacturer
MC56F8323PB Datasheet PDF : 124 Pages
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MC56F8323/D
Rev. 2.0 09/2003
56F8323
Preliminary Technical Data
56F8323 16-bit Hybrid Controller
• Up to 60 MIPS at 60MHz core frequency
• One Quadrature Decoder
• DSP and MCU functionality in a unified,
C-efficient architecture
• 32KB Program Flash
• 4KB Program RAM
• 8KB Data Flash
• 8KB Data RAM
• 8KB Boot Flash
• One 6-channel PWM Module
• One FlexCAN Module
• Up to two Serial Communication Interfaces (SCIs)
• Up to two Serial Peripheral Interfaces (SPIs)
• Two General Purpose Quad Timers
• Computer Operating Properly (COP)/Watchdog
• On-Chip Relaxation Oscillator
• JTAG/Enhanced On-Chip Emulation (OnCE™) for
unobtrusive, real-time debugging
• Two 4-channel 12-bit ADCs
• Up to 27 GPIO lines
• Temperature Sensor
• 64-pin LQFP Package
RESET
OCR_DIS VCAP VDD VSS VDDA VSSA
5
4
44
2
3
3
6 PWM Outputs
PWMA or
Current Sense Inputs SPI1 or
Fault Inputs
GPIOA
JTAG/
EOnCE
Port
Digital Reg Analog Reg
16-Bit
56800E Core
Low Voltage
Supervisor
Program Controller
Address
and Hardware Generation Unit
Data ALU
16 x 16 + 36 → 36-Bit MAC
Bit
Manipulation
Looping Unit
Three 16-bit Input Registers
Four 36-bit Accumulators
Unit
4
AD0
4
AD1
5
VREF
Memory
Program Memory
16K x 16 Flash
XDB2
XAB1
XAB2
Temp_Sense
Boot ROM
4K x 16 Flash
Data Memory
Quadrature 4K x 16 Flash
4
Decoder 0 or
Quad
Timer A or
GPIO B
PAB
PDB
CDBR
CDBW
PAB
PDB
CDBR
CDBW
R/W Control
System Bus
Control
IPBus Bridge (IPBB)
Quad
3
Timer C or
SCI0 or
GPIOC Decoding
Peripheral
Device Selects
RW IPAB IPWDB
Control
IPRDB
2
Peripherals
FlexCAN or
GPIOC
Clock
resets
PLL
SPI0 or
SCI1 or
GPIOB
4
COP/
Interrupt
Watchdog Controller
IRQA
System
P
O
Integration R
Module
Clock
Generator*
O
S
C
XTAL or GPIOC
EXTAL or GPIOC
*Includes On-Chip
Relaxation Oscillator
56F8323 Block Diagram
© Motorola, Inc., 2003. All rights reserved.
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