NT68P61AU View Datasheet(PDF) - Unspecified
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NT68P61AU Datasheet PDF : 48 Pages
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NT68P61A
8. PWM DACs (Pulse Width Modulation D/A Converters)
There are 14 PWM D/A converters with 8-bit resolution in NT68P61A. Eight of these D/A (DAC0 - DAC7) converters are
open-drain output structures with 12V applied (maximum), and the other six D/A converters (DAC8 - DAC13) are
open-drain output structures with 5V applied (maximum). The PWM frequency is 31.25 KHz on 8 MHz system clock. Use
of a different oscillator frequency will result in different PWM frequency. As DAC8 - DAC13 are shared with I/O port pins,
user can write '0' to corresponding enable bit in the ENDAC control register to activate each of DACH8 - 13. There are 14-
channel readable DACH registers corresponding to 14 D/A converters. Each PWM output pulse width is programmable by
setting the 8 bit digital to the corresponding DACH registers. When these DACH registers are set to 00H, the DAC will
output LOW (GND level) and each bit addition will add 125ns pulse width. After reset, all DAC outputs are set to 80H (1/2
duty output). Refer to Figure 4 for the detailed timing diagram of PWM D/A output.
8MHz Fosc
PWM value: 255
0
1
2
00
m
m+1
m+2
255
0
1
01
02
m
255 (FF)
Figure 4. The DAC Output Timing Diagram and Wave Table
DKVL7
0
0
0
0
0
-
-
-
1
1
DKVL6
0
0
0
0
0
-
-
-
1
1
DKVL5
0
0
0
0
0
-
-
-
1
1
DKVL4
0
0
0
0
0
-
-
-
1
1
DKVL3
0
0
0
0
0
-
-
-
1
1
The DAC value correspondent to PWM output
DKVL2
0
0
0
0
1
-
-
-
1
1
DKVL1
0
0
1
1
0
-
-
-
1
1
DKVL0
0
1
0
1
0
-
-
-
0
1
* Vref. is 12V or 5V
DAC Output Duty Cycle
GND
1/256 Vref.
2/256 Vref.
3/256 Vref.
4/256 Vref.
X /256 Vref.
254/256 Vref.
255/256 Vref.
18
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