PEB20321 View Datasheet(PDF) - Siemens AG

Part Name

Description

Manufacturer

PEB20321

Multichannel Network Interface Controller for HDLC MUNICH32X

Siemens AG 

PEB 20321

Introduction

Table 1

PCI Bus Interface Pins (cont’d)

Pin No. Pin No. Symbol I/O

P-MQFP- P-TQFP-

160-1

176-1

13

15

PAR

t/s

3

5

FRAME s/t/s

Function

Parity

PAR is even parity across AD(31:0) and

C/BE(3:0). PAR is stable and valid one

clock after the address phase. PAR has the

same timing as AD(31:0) but delayed by

one clock.

When MUNICH32X is Master, PAR is

output during address phase and write data

phases. When MUNICH32X is Slave, PAR

is output during read data phases.

Parity errors detected by the MUNICH32X

are indicated on PERR output.

PAR is updated and sampled on the rising

edge of CLK.

Frame

FRAME indicates the beginning and end of

an access. FRAME is asserted to indicate a

bus transaction is beginning. While FRAME

is asserted, data transfers continue. When

FRAME is deasserted, the transaction is in

the final phase.

When MUNICH32X is Master, FRAME is

an output.

When MUNICH32X is Slave, FRAME is an

input.

FRAME is updated and sampled on the

rising edge of CLK.

Semiconductor Group

16

1998-08-01

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