RM7000-250T View Datasheet(PDF) - PMC-Sierra

Part Name

Description

Manufacturer

RM7000-250T

RM7000™ Microprocessor with On-Chip Secondary Cache Datasheet Released

PMC-Sierra 

RM7000A™ Microprocessor with On-Chip Secondary Cache Datasheet

Released

List of Tables

Table 1 Instruction Issue Rules ...............................................................................................12

Table 2 Dual Issue Instruction Classes ...................................................................................13

Table 3 ALU Operations .........................................................................................................15

Table 4 Integer Multiply/Divide Operations ..............................................................................15

Table 5 Floating Point Latencies and Repeat Rates ...............................................................17

Table 6 Cache Attributes .........................................................................................................26

Table 7 Cache Locking Control ...............................................................................................26

Table 8 Penalty Cycles ............................................................................................................27

Table 9 Watch Control Register ...............................................................................................33

Table 10 Performance Counter Control .....................................................................................34

Table 11 Cause Register ...........................................................................................................36

Table 12 Interrupt Control Register ...........................................................................................36

Table 13 IPLLO Register ...........................................................................................................36

Table 14 IPLHI Register ............................................................................................................36

Table 15 Interrupt Vector Spacing .............................................................................................37

Table 16 Boot Time Mode Stream .............................................................................................38

Table 17 System interface Pins .................................................................................................39

Table 18 Clock/control interface Pins ........................................................................................40

Table 19 Tertiary cache interfacePins .......................................................................................41

Table 20 Interrupt Interface Pins ...............................................................................................42

Table 21 JTAG Interface Pins ....................................................................................................42

Table 22 Initialization Interface Pins ..........................................................................................42

Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use

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Document ID: PMC-2002175, Issue 1

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