0.0130"
(0.335mm)
0.0275" 0.0365" 0.0465"
(0.700mm) (0.930mm) (1.180mm)
0.0575"
(1.465mm)
0.0249"
(0.630mm)
0.0299"
(0.760mm)
0.0189"
(0.480mm)
0.013"
(0.330mm)
0.0
0.0
0.004"
(0.1mm)
0.0168"
0.028"
(0.430mm) (0.715mm)
0.0475"
(1.200mm)
Back of Chip is RF and DC Ground
0.0185"
(0.465mm)
0.0125"
(0.315mm)
0.0065"
(0.165mm)
0.004"
(0.1mm)
0.0677"
(1.70mm)
0.0064"
(1.620mm)
Figure 2. Chip Layout and Bond Pad Locations
Chip Size = 0.0677" x 0.30" x 0.002" (1720µm x 760µm x 50µm)
BOND WIRE Ls
10,000 pF
DRAIN SUPPLY (Vd)
(Connect to both Vd1 & Vd3)
100 pF
RF IN
MMIC Chip
Vd1 Vg2 alt
Vd2
Vd3
Vd4
Vg1
Vg2
Vg3
Vg4
RF OUT
GROUND
(Back of Chip)
100 pF
BOND WIRE Ls
Note: The Input does not have a
DC blocking capacitor. It is
terminated with a 50Ω
resistor to ground on chip and it
is isolated from any DC bias.
10,000 pF
GATE SUPPLY (Vg)
(VGA and/or VGB)
Note: For currents > 370 mA connect
all four drain pads to the 100pF
capacitor.
Figure 3. Schematic of Application Circuit
©2004 Fairchild Semiconductor Corporation
RMDA20420 Rev. D