SP502 View Datasheet(PDF) - Signal Processing Technologies

Part Name

Description

Manufacturer

SP502

Multi–Mode Serial Transceiver

Signal Processing Technologies 

Pin 78 — DSR— Data Set Ready; TTL output;

sourced from DM(a), DM(b) inputs.

Pin 80 — CTS— Clear To Send; TTL output;

sourced from CS(a) and CS(b) inputs.

CONTROL REGISTERS

Pins 2–5 — RDEC0 – RDEC3 — Receiver

decode register; configures receiver modes; TTL

inputs.

Pin 6 — ST/TT — Enables ST or TT drivers,

TTL input.

Pins 12–9 — TDEC0 – TDEC3 — Transmitter

decode register; configures transmitter modes;

TTL inputs.

POWER SUPPLIES

Pins 8, 25, 33, 41, 48, 55, 62, 73, 74 — VCC —

+5V input.

Pins 7, 29, 34, 43, 46, 50, 53, 57, 60, 64, 72, 75

— GND — Ground.

Pin 27 — VDD +10V Charge Pump Capacitor —

Connects from VDD to VCC. Suggested capaci-

tor size is 22µF, 16V.

Pin 32 — VSS –10V Charge Pump Capacitor —

Connects from ground to VSS. Suggested ca-

pacitor size is 22µF, 16V.

Pins 26 and 30 — C1+ and C1–

Capacitor — Connects from

— Charge

C1+ to C1–.

Pump

Sug-

gested capacitor size is 22µF, 16V.

Pins 28 and 31 — C2+ and C2–

Capacitor — Connects from

— Charge

C2+ to C2–.

Pump

Sug-

gested capacitor size is 22µF, 16V.

NOTE: NC pins should be left floating; internal

signals may be present.

FEATURES…

The SP502 is a highly integrated serial trans-

ceiver that allows software control of its inter-

face modes. The SP502 offers hardware inter-

face modes for RS-232 (V.28), RS-422A (V.11),

RS-449, RS-485, V.35, and EIA-530. The inter-

face mode selection is done via an 8–bit switch;

four (4) bits control the drivers and four (4) bits

control the receivers. The SP502 is fabricated

using low–power BiCMOS process technology,

and incorporates a Sipex patented (5,306,954)

charge pump allowing +5V only operation. Each

device is packaged in an 80–pin Quad FlatPack

package.

The SP502 is ideally suited for wide area net-

work connectivity based on the interface modes

offered and the driver and receiver configura-

tions. The SP502 has five (5) independent driv-

ers and six (6) independent receivers and one

half–duplex transceiver channel, which allows

a maximum of six (6) drivers and seven (7)

receivers. The driver and receiver configuration

for the SP502 is ideal for DTE applications. The

SP502 is made up of four separate circuit blocks

– the charge pump, drivers, receivers, and

decoder. Each of these circuit blocks is de-

scribed in detail below.

THEORY OF OPERATION

Charge–Pump

The charge pump is a Sipex patented design

(5,306,954) and uses a unique approach com-

pared to older less efficient designs. The charge

pump still requires four external capacitors, but

uses a four–phase voltage shifting technique to

attain symmetrical 10V power supplies. Figure

3a shows the waveform found on the positive

side of capcitor C2, and Figure 3b shows the

negative side of capcitor C2. There is a free–

running oscillator that controls the four phases

of the voltage shifting. A description of each

phase follows.

Phase 1

— VSS charge storage —During this phase of

the clock cycle, the positive side of capacitors

C1 and C2 are

then switched

is transferred

ttioonigCtriao2–lul.ynSdcihnanacredgteChd2e+tcoihs+arc5goVen.onCnecl+Cte1ids–

to +5V, the voltage potential across capacitor

C2 is now 10V.

Phase 2

— VSS transfer — Phase two of the clock con-

nects the negative terminal of C2 to the VSS

storage capacitor and the positive terminal of C2

to ground, and transfers the generated –l0V to

C3. Simultaneously, the positive side of capaci-

Rev. 7/21/03

SP502 Multi-Mode Serial Transceiver

8

© Copyright 2003 Sipex Corporation

Share Link: