SSD1812 View Datasheet(PDF) - Unspecified

Part Name

Description

Manufacturer

SSD1812

LCD Segment / Common Driver with Controller

Unspecified 

OPERATION OF LIQUID CRYSTAL DISPLAY DRIVER

Description of Block Diagram Module

Command Decoder and Command Interface

This module determines whether the input data is interpreted as

data or command. Data is directed to this module based upon the

input of the D/C pin. If D/C is high, data is written to Graphic Display

Data RAM (GDDRAM). If D/C is low, the input at D0-D7 is interpreted

as a Command and it will be decoded and written to the correspond-

ing command register.

Reset is of the same function as Power ON Reset (POR). Once

RES receives a negative reset pulse of about 1us, all internal circuitry

will be back to its initial status. Refer to Command Description section

for more information.

MPU Parallel 6800-series Interface

The parallel interface consists of 8 bi-directional data pins (D0-D7),

R/W(WR), D/C, E(RD), CS1 and CS2. R/W(WR) input High indicates

a read operation from the Graphic Display Data RAM (GDDRAM) or

the status register. R/W(WR) input Low indicates a write operation to

Display Data RAM or Internal Command Registers depending on the

status of D/C input. The E(RD) input serves as data latch signal

(clock) when high provided that CS1 and CS2 are low and high

respectively. Refer to Figure 1 of parallel timing characteristics for

Parallel Interface Timing Diagram of 6800-series microprocessors.

In order to match the operating frequency of display RAM with that

of the microprocessor, some pipeline processing is internally per-

formed which requires the insertion of a dummy read before the first

actual display data read. This is shown in Figure 4 below.

MPU Parallel 8080-series interface

The parallel interface consists of 8 bi-directional data pins (D0-D7),

E(RD), R/W(WR), D/C, CS1 and CS2. E(RD) input serves as data

read latch signal (clock) when low provided that CS1 and CS2 are

low and high respectively. Whether it is display data or status regis-

ter read is controlled by D/C. R/W(WR) input serves as data write

latch signal(clock) when high provided that CS1 and CS2 are low

and high respectively. Whether it is display data or command regis-

ter write is controlled by D/C. Refer to Figure 2 of parallel timing

characteristics for Parallel Interface Timing Diagram of 8080-series

microprocessor.

Similar to 6800-series interface, a dummy read is also required

before the first actual display data read.

MPU Serial interface

The serial interface consists of serial clock SCK, serial data SDA,

D/C, CS1 and CS2. SDA is shifted into a 8-bit shift register on every

rising edge of SCL in the order of D7, D6,... D0. D/C is sampled on

every eighth clock and the data byte in the shift register is written to

the Display Data RAM or command register in the same clock.

R/W(WR)

E(RD)

data bus

N

write column address

dummy read

n

data read1

n+1

data read 2

n+2

data read 3

Figure 4: display data read with the insertion of dummy read

Graphic Display Data RAM (GDDRAM)

The GDDRAM is a bit mapped static RAM holding the bit pattern

to be displayed. The size of the RAM is 132 x 65= 8580 bits. Figure 5

is a description of the GDDRAM address map. For mechanical flexi-

bility, re-mapping on both Segment and Common outputs are pro-

vided. For vertical scrolling of display, an internal register storing the

display start line can be set to control the portion of the RAM data to

be mapped to the display. Figure 5 shows the case in which the dis-

play start line register is set at 38H.

SOLOMON

REV 1.2 SSD1812

12/99

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