TC9028AP View Datasheet(PDF) - Toshiba

Part Name

Description

Manufacturer

TC9028AP

TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic

Toshiba 

3.2.1

Timer register (TR)

The timer register is a 4bit write-only register.

It selects the mode when the timer status is read.

The timer register is initialized to 0 at reset.

TC9028AP/AF

3

2

1

0

IBNS

TIBS

(Initial value: 0000)

Selects number of bits to be read as timer status

0: Read 1 bit data from P53 (IT3)

At this time, the P52 to P50 data (IT2 to IT0) are 0.

1: Read 4 bit data from P53 to P50 (IT3 to IT0)

The cycle for each bit is as follows.

(Fixed)

P53: 215/fc

P52: 214/fc

P51: 213/fc

P50: 212/fc

Figure 3.4

Selects timer cycle/duty

Valid only when IBNS is 0

000: Cycle 210/fc, duty 50%

001: Cycle 211/fc, duty 50%

010: Cycle 211/fc, duty 75%

011: Cycle 212/fc, duty 50%

100: Cycle 212/fc, duty 75%

101: Cycle 213/fc, duty 50%

110: Cycle 213/fc, duty 75%

111: Cycle 214/fc, duty 50%

Timer/counter output mode control using timer register

11

2002-04-19

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