TS68HC901CFN8 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

TS68HC901CFN8

HCMOS MULTI-FUNCTION PERIPHERAL

STMicroelectronics 

TS68HC901

Figure 3 : PDIP Pin connection

Figure 4 : PLCC Pin connection

Pin MOTOROLA MOTOROLA

6800 Type Multiplexed

48

CS

CS

47

E

DS

1

R/W

R/W

35

VSS

AS

INTEL

CS

RD

WR

ALE

PIN DESCRIPTION

GND : Ground

VCC : +5 volts (± 5%)

R/W :

Read/Write (input). This input defines a

data transfert as a Read (High) or Write

(Low) cycle. This signal is used as WR

with an Intel processor type.

DTACK : This output signals the completion of the

operation phase of a bus cycle to the pro-

cessor. If the bus cycle is a processor

read, the CMFP asserts DTACK to indi-

cate that the information on the Data bus

is valid. If the bus cycle is a processor to

the CMFP, DTACK acknowledges the

acceptance of the data by the CMFP.

DTACK will be asserted only by an CMFP

that has CS or IAK (and IEI) asserted.

This signal is not used with a 6800 pro-

cessor type.

CS :

DS :

Chip Select (input, active low). CS is u-

sed to select the TS68HC901 CMFP for

accesses to the internal registers. CS

and IACK must not be asserted at the

same time.

Data Stobe (input, active low).This Input

is part of the internal chip select and in-

terrupt acknowledge functions.

The CMFP must be located on the lower

portion of the 16-bit data-bus so that the

vector number passed to the processor

during an interrupt acknowledge cycle

will be located in the low byte of the data

word. As a result, DS must be connected

to the processor’s lower data strobe if

vectored interrupt are to be used. Note

that this forces all registers to be located

at odd addresses and latches data on the

rising edge for writes. This signal is used

as RD with an Intel processor type.

4/42

®

Share Link: