ST24LC21B1TR View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
ST24LC21B1TR Datasheet PDF : 18 Pages
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ST24LC21
Figure 4. Transition Mode Waveforms
SCL
SDA
VCLK
Transmit Only Mode
Bi-Directional Mode
AI01502
Transmit Only Mode
After a Power-up, the device is in the Transmit Only
mode. A proper initialization sequence must supply
nine clock pulses on the VCLK pin (in order to
internally synchronize the device). During this in-
itialization sequence, the SDA pin is in high imped-
ance. On the rising edge of the tenth pulse applied
on VCLK pin, the device will output the first bit of
byte located at address 00h (most significant bit
first).
A byte is clocked out (on SDA pin) with nine clock
pulses on VCLK: 8 clock pulses for the data byte
and one extra clock pulse for a Don’t Care bit.
As long as the SCL pin is held high, each byte of
the memory array is transmitted serially on the SDA
pin with an automatic address increment.
When the last byte is transmitted, the address
counter will roll-over to location 00h.
I2C Bidirectional Mode
The device can be switched from Transmit Only
mode to I2C Bidirectional mode by applying a valid
high to low transition on the SCL pin (see Figure 4).
When the device is in the I2C Bidirectional mode,
the VCLK input enables (or inhibits) the execution
of any write instruction: if VCLK = 1, write instruc-
tions are executed; if VCLK = 0, write instructions
are not executed.
The device is compatible with the I2C standard, two
wire serial interface which uses a bi-directional data
bus and serial clock. The device carries a built-in 4
bit, unique device identification code (1010) corre-
sponding to the I2C bus definition.
The device behaves as a slave device in the I2C
protocol with all memory operations synchronized
by the serial clock. Read and write operations are
initiated by a START condition generated by the
bus master. The START condition is followed by a
stream of 7 bits (identification code 1010XXX), plus
one read/write bit and terminated by an acknow-
ledge bit.
When writing data to the memory it responds to the
8 bits received by asserting an acknowledge bit
during the 9th bit time. When data is read by the
bus master, it acknowledges the receipt of the data
bytes in the same way. Data transfers are termi-
nated with a STOP condition.
Power On Reset: VCC lock out write protect. In
order to prevent data corruption and inadvertent
write operations during power up, a Power On
Reset (POR) circuit is implemented. Until the VCC
voltage has reached the POR threshold value, the
internal reset is active, all operations are disabled
and the device will not respond to any command.
In the same way, when VCC drops down from the
operating voltage to below the POR threshold
value, all operations are disabled and the device
will not respond to any command. A stable VCC
must be applied before applying any logic signal.
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