GAL16V8B-20LJ View Datasheet(PDF) - Lattice Semiconductor

Part Name

Description

Manufacturer

GAL16V8B-20LJ

High Performance E2CMOS PLD Generic Array Logic™

Lattice Semiconductor 

Specifications GAL16V8

REGISTERED MODE

In the Registered mode, macrocells are configured as dedicated

registered outputs or as I/O functions.

Architecture configurations available in this mode are similar to

the common 16R8 and 16RP4 devices with various permutations

of polarity, I/O and register placement.

All registered macrocells share common clock and output enable

control pins. Any macrocell can be configured as registered or

I/O. Up to eight registers or up to eight I/O's are possible in this

mode. Dedicated input or output functions can be implemented

as subsets of the I/O function.

Registered outputs have eight product terms per output. I/O's

have seven product terms per output.

The JEDEC fuse numbers, including the User Electronic Signature

(UES) fuses and the Product Term Disable (PTD) fuses, are

shown on the logic diagram on the following page.

CLK

DQ

XOR

Q

OE

XOR

Registered Configuration for Registered Mode

- SYN=0.

- AC0=1.

- XOR=0 defines Active Low Output.

- XOR=1 defines Active High Output.

- AC1=0 defines this output configuration.

- Pin 1 controls common CLK for the registered outputs.

- Pin 11 controls common OE for the registered outputs.

- Pin 1 & Pin 11 are permanently configured as CLK &

OE.

Combinatorial Configuration for Registered Mode

- SYN=0.

- AC0=1.

- XOR=0 defines Active Low Output.

- XOR=1 defines Active High Output.

- AC1=1 defines this output configuration.

- Pin 1 & Pin 11 are permanently configured as CLK &

OE.

Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.

3-68

1996 Data Book

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