AD1895YRS View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
AD1895YRS Datasheet PDF : 24 Pages
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DIGITAL TIMING (–40؇C < TA < +105؇C, VDD_CORE = 3.3 V ؎ 5%, VDD_IO = 5.0 V ؎ 10%)
Parameter1
Min
tMCLKI
MCLK_I Period
33.3
fMCLK
MCLK_I Frequency
tMPWH
MCLK_I Pulsewidth High
8
tMPWL
MCLK_I Pulsewidth Low
12
Input Serial Port Timing
tLRIS
LRCLK_I Setup to SCLK_I
8
tSIH
SCLK_I Pulsewidth High
8
tSIL
SCLK_I Pulsewidth Low
8
tDIS
SDATA_I Setup to SCLK_I Rising Edge
8
tDIH
SDATA_I Hold from SCLK_I Rising Edge
3
Output Serial Port Timing
tTDMS
tTDMH
tDOPD
tDOH
tLROS
tLROH
tSOH
tSOL
tRSTL
TDM_IN Setup to SCLK_O Falling Edge
3
TDM_IN Hold from SCLK_O Falling Edge
3
SDATA_O Propagation Delay from SCLK_O, LRCLK_O
SDATA_O Hold from SCLK_O
3
LRCLK_O Setup to SCLK_O (TDM Mode Only)
5
LRCLK_O Hold from SCLK_O (TDM Mode Only)
3
SCLK_O Pulsewidth High
10
SCLK_O Pulsewidth Low
5
RESET Pulsewidth LO
NOTES
1Refer to Timing Diagram Section.
2The maximum possible sample rate is: FSMAX = fMCLK /138.
3fMCLK of up to 34 MHz is possible under the following conditions: 0°C < TA < 70°C, 45/55 or better MCLK_I duty cycle.
Specifications subject to change without notice.
Max
30.02, 3
20
200
TIMING DIAGRAMS
LRCLK_I
SCLK I
SDATA I
tLRIS
tDIS
tDIH
tSIH
tSIL
LRCLK O
SCLK O
tDOPD
SDATA O
LRCLK O
tLROS
tLROH
tSOH
tSOL
tDOH
SCLK O
TDM IN
tTDMS
tTDMH
Figure 1. Input and Output Serial Port Timing (SCLK I/O,
LRCLK I/O, SDATA I/O, TDM_IN)
MCLK I
RESET
tRSTL
Figure 2. RESET Timing
tMPWH
tMPWL
Figure 3. MCLK_I Timing
AD1895
Unit
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
REV. A
–3–
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