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ILC6377 View Datasheet(PDF) - Impala Linear Corporation

Part Name
Description
Manufacturer
ILC6377 Datasheet PDF : 11 Pages
1 2 3 4 5 6 7 8 9 10
0.5A, 300kHz, SO-8 PWM/PFM Step Down Converter with Shutdown
VI N
S/D
EXT1
*CI N +
1
8
2 ILC6377 7
3
6
(TOP VIE W)
4
5
CSS
SD1
L
+
CL
VO UT
Fig. 2: 1AmpFoigut.p2u1t Acumrrepnot uaptppluictatciounrruesnintgaepxptelrincaaltMioOnSFET
using external MOSFET
The EXT1 and EXT2 pins are provided so as to drive
external transistors; thus allowing design flexibility.
The EXT output drive signal has the same timing as
the gate drive to the internal P-channel MOSFET i.e.
EXT output is low as long as the internal MOSFET is
on. Both EXT1 and EXT2 pins are capable of driving
1000pF gate capacitance. For example, a high out-
put current application circuit using an external P-
channel MOSFET is shown in figure 2.
To pin 8
6 CF B
5
VOU T
RFB1
RFB 1 + RF B2 2M
RFB2
CF B
chosen
so that 1kHz
<
-------------------------1----------------------------
2 × π × CF B × RFB1
< 20kHz
Fig.4FigA.d4j:uAsdtajubstleaboleuotuptuptutuussiinngg IILLCC6367377S7OS-AOd-jAdj
( N(Nootete:: rreessttoof fcicrcirucituisit siasmseaamsefigausreF1i)g.1 )
Adjustable Output ( ILC6377SO-Adj )
For adjustable output voltage ILC6377SO-Adj should be
used. All connections to the ILC6377SO-Adj are the same
as ILC6377SO-XX, except for the feedback voltage divider
network shown in figure 4. The output voltage, VOUT, can be
calculated from the following equation:
VOUT = VFB ( 1 + RFB1/RFB2 ),
where VFB is approximately 1V and
RFB1 + RFB2 < 2M
CBST
2200pF
SD1
MA729
Schottky
1
8
2 ILC6377 7
3
6
(TOP VI EW)
4
5
Voltage beettwweeeenn VVIiNnaannddP_BST
must be less than 10V.
FigFuirge. 33:. PP-C-hCahnannelnNeelgNateivgeative
P-Channel Boost Circuit
The ILC6377 includes a unique P-Channel MOSFET
architecture with built-in charge pump to maintain low
on-resistance even at low input voltages. As shown in
figure 3, a 2200pF ceramic capacitor and a schottky
diode ( MA729 or equivalent ) allows the gate voltage
of the internal P-Channel MOSFET to be driven neg-
ative; thus reducing the switch on-resistance. This
technique can be employed to increase efficiency at
low input voltages and high output currents.
Note that the voltage between VIN and P_BST should not
exceed 10V, otherwise damage to the device may occur.
For high input voltage applications the schottky diode
should be replaced by a low voltage zener diode so that the
P_BST pin is clamped to a safe negative voltage.
The feedback compensation capacitor should be chosen
such that the pole frequency f is between 1kHz and 20kHz:
1kHz<
1
<20kHz
2 x Π X CFB X RFB1
The pole frequency should generally be set at 5kHz. The
value of CFB calculated from the above equation may
require some adjustment depending on the output inductor
( L ) and output capacitor ( CL ) values chosen.
Example for 3V output :
RFB1 = 400k
RFB2 = 200k
CFB = 100pF
PC Board Layout
As with all switching DC-DC converter designs, good PC
board layout is critical for optimum performance. The heavy
lines indicated in figure 1 schematic should be wide
printed circuit board traces and should be kept as short
as is practical. A large ground plane with as much copper
area as is allowable should be used. All external compo-
nents should be mounted as close to the IC as possible. For
ILC6377SO-Adj, the feedback resistors and their associat-
ed wiring should be kept away from the inductor location
and the vicinity of inductive flux.
Impala Linear Corporation
ILC6377 1.3
(408) 574-3939 www.impalalinear.com
June 1999 6

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