M68Z512 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
M68Z512 Datasheet PDF : 16 Pages
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M68Z512
DESCRIPTION
The M68Z512 is a 4 Mbit (4,194,304 bit) CMOS
SRAM, organized as 524,288 words by 8 bits. The
device features fully static operation requiring no
external clocks or timing strobes, with equal ad-
dress access and cycle times. It requires a single
5V ±10% supply, and all inputs and outputs are
TTL compatible.
This device has an automatic power-down feature,
reducing the power consumption by over 99%
when deselected.
The M68Z512 is available in a 32-lead TSOP II
(10 x 20mm) package.
Figure 2. Logic Diagram
VCC
19
A0-A18
8
DQ0-DQ7
W
M68Z512
E
G
Table 1. Signal Names
A0-A18
Address Inputs
DQ0-DQ7
Data Input/Output
E
Chip Enable
G
Output Enable
W
Write Enable
VCC
Supply Voltage
VSS
Ground
VSS
AI03030
Figure 3. TSOP Connections
A17
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
1
32
8
M68Z512 25
9
24
16
17
VCC
A15
A18
W
A13
A8
A9
A11
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
AI03031
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