MT4C1004J883C View Datasheet(PDF) - Austin Semiconductor
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Description
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MT4C1004J883C Datasheet PDF : 14 Pages
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AUSTIN SEMICONDUCTOR, INC.
MMTT45CC1100045J 883C
4 M25E6GK xx 14 DSRAM
boundary. The FAST PAGE MODE cycle is always initi-
ated with a row address strobed-in by /R/A/S followed by a
column address strobed-inby C/ /A/S. /C/A/S may be toggled-in
by holding /R/A/S LOW and strobing-in different column
addresses, thus executing faster memory cycles. Returning
/R/A/S HIGH terminates the FAST PAGE MODE operation.
Returning /R/A/S and /C/A/S HIGH terminates a memory cycle
and decreases chip current to a reduced standby level. Also,
the chip is preconditioned for the next cycle during the /R/A/
S HIGH time. Memory cell data is retained in its correct state
by maintaining power and executing any /R?A/S cycle (READ,
WRITE, /R?A/S-ONLY, /C/A/S-BEFORE-/R/A/S, or HIDDEN RE-
FRESH) so that all 1,024 combinations of /R?A/S addresses
(A0 -A9) are executed at least every 16ms, regardless of
sequence. The /C?A/S - BEFORE-/R?A/S cycle will invoke the
refresh counter for automatic /R/?A/S addressing.
FUNCTIONAL BLOCK DIAGRAM
FAST PAGE MODE
WE
CAS
NO. 2 CLOCK
GENERATOR
*EARLY-WRITE
DETECTION CIRCUIT
DATA IN
D
BUFFER
DATA OUT
Q
BUFFER
COLUMN
A0
11
ADDRESS
BUFFER(11)
A1
A2
REFRESH
A3
CONTROLLER
A4
A5
A6
REFRESH
A7
COUNTER
A8
10
A9
A10
ROW
11
ADDRESS
BUFFERS (11)
11
COLUMN
DECODER
4096
SENSE AMPLIFIERS
I/O GATING
4096
1
MEMORY
10
1024
ARRAY
RAS
NO. 1 CLOCK
GENERATOR
Vcc
Vss
*NOTE: WE LOW prior to CAS LOW, EW detection circuit output is a HIGH (EARLY-WRITE)
CAS LOW prior to WE LOW, EW detection circuit output is a LOW (LATE-WRITE)
MT4C1004J 883C
REV. 11/97
DS000021
2-24
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
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