IS43TR16128A View Datasheet(PDF) - Integrated Silicon Solution
Part Name
Description
Manufacturer
IS43TR16128A Datasheet PDF : 88 Pages
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IS43/46TR16128A, IS43/46TR16128AL,
IS43/46TR82560A, IS43/46TR82560AL
3.4 Thermal Resistance
Package
Substrate
78-ball
96-ball
4-layer
4-layer
Theta-ja
(Airflow = 0m/s)
45.2
29.4
Theta-ja
(Airflow = 1m/s)
35.8
24.5
Theta-ja
(Airflow = 2m/s)
33.4
23.1
4. AC & DC INPUT MEASUREMENT LEVELS
Theta-jc
5.3
3.3
Units
C/W
C/W
4.1. AC and DC Logic Input Levels for Single-Ended Signals
4.1.1 AC and DC Input Levels for Single-Ended Command and Address Signals
Symbol
Parameter
DDR3-800/1066/1333/1600
Min.
Max.
DDR3-1866/2133
Min.
Max.
VIH.CA(DC100) DC input logic high Vref + 0.100
VDD
Vref + 0.100
VDD
VIL.CA(DC100) DC input logic low
VSS
Vref - 0.100
VSS
Vref - 0.100
VIH.CA(AC175) AC input logic high Vref + 0.175
Note2
--
--
VIL.CA(AC175) AC input logic low
Note2
Vref - 0.175
--
--
VIH.CA(AC150) AC input logic high Vref + 0.150
Note2
--
--
VIL.CA(AC150) AC input logic low
Note2
Vref - 0.150
--
--
VIH.CA(AC135) AC input logic high
--
--
Vref + 0.135
Note2
VIL.CA(AC135) AC input logic low
--
--
Note2
Vref - 0.135
VIH.CA(AC125) AC input logic high
--
--
Vref + 0.125
Note2
VIL.CA(AC125)
VREFCA(DC)
AC input logic low
Reference Voltage for
ADD, CMD inputs
--
0.49 * VDD
--
0.51* VDD
Note2
0.49 * VDD
Vref - 0.125
0.51* VDD
Units
V
V
V
V
V
V
V
V
V
V
V
V
Note
1
1
1, 2, 5
1, 2, 5
1, 2, 5
1, 2, 5
1, 2, 5
1, 2, 5
1, 2, 5
1, 2, 5
1, 2, 5
3, 4
Symbol
VIH.CA(DC90)
VIL.CA(DC90)
VIH.CA(AC160)
VIL.CA(AC160)
VIH.CA(AC135)
VIL.CA(AC135)
VIH.CA(AC125)
VIL.CA(AC125)
VREFCA(DC)
Parameter
DC input logic high
DC input logic low
AC input logic high
AC input logic low
AC input logic high
AC input logic low
AC input logic high
AC input logic low
Reference Voltage for
ADD, CMD inputs
DDR3L-800/1066/1333/1600
Min.
Max.
Vref + 0.09
VDD
VSS
Vref + 0.16
Note2
Vref + 0.135
Note2
--
--
Vref - 0.09
Note2
Vref - 0.160
Note2
Vref - 0.135
--
--
0.49 * VDD
0.51* VDD
DDR3L-1866
Min.
Max.
Vref + 0.09
VDD
VSS
--
--
Vref + 0.135
Note2
Vref + 0.125
Note2
Vref - 0.09
--
--
Note2
Vref - 0.135
Note2
Vref - 0.125
0.49 * VDD
0.51* VDD
Units
V
V
V
V
V
V
V
V
V
V
Note
1
1
1, 2, 5
1, 2, 5
1, 2, 5
1, 2, 5
1, 2, 5
1, 2, 5
1, 2, 5
3, 4
Notes:
1. For input only pins except RESET.Vref=VrefCA(DC)
2. See "Overshoot and Undershoot Specifications"
3. The ac peak noise on Vref may not allow Vref to deviate from Vref(DC) by more than +/- 1.0% VDD.
4. For reference: DDR3 has approx. VDD/2 +/- 15mV, DDR3L has approx VDD/2 +/- 13.5mV.
5. To allow VREFCA margining, all DRAM Command and Address Input Buffers MUST use external VREF (provided by system) as the input for their
VREFCA pins. All VIH/L input level MUST be compared with the external VREF level at the 1st stage of the Command and Address input buffer
Integrated Silicon Solution, Inc. – www.issi.com –
30
Rev. G
09/28/2015
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