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IS43TR16640A-15GBLI View Datasheet(PDF) - Unspecified

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IS43TR16640A-15GBLI
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Unspecified ETC
IS43TR16640A-15GBLI Datasheet PDF : 88 Pages
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IS43/46TR16640A, IS43/46TR16640AL
IS43/46TR81280A, IS43/46TR81280AL
4.2 Vref Tolerances
The dc-tolerance limits and ac-moist limits for the reference voltages VrefCA and VrefDQ are illustrated in the following
figure. It shows a valid reference voltage Vref(t) as a function of time. (Vref stands for VrefCA and VrefDQ likewise).
Vref(DC) is the linear average of Vref(t) over a very long period of time (e.g.,1 sec). This average has to meet the min/max
requirement in previous page. Furthermore Vref(t) may temporarily deviate from Vref(DC) by no more than ±1% VDD.
The voltage levels for setup and hold time measurements VIH(AC), VIH(DC), VIL(AC), and VIL(DC) are dependent on
Vref. “Vref” shall be understood as Vref(DC). The clarifies that dc-variations of Vref affect the absolute voltage a signal
has to reach to achieve a valid high or low level and therefore the time to which setup and hold is measured. System
timing and voltage budgets need to account for Vref(DC) deviations from the optimum position within the data-eye of the
input signals.
This also clarifies that the DRAM setup/hold specification and de-rating values need to include time and voltage
associated with Vref ac-noise. Timing and voltage effects due to ac-noise on Vref up to the specified limit (±1% of VDD)
are included in DRAM timing and their associated de-ratings.
Figure 4.2 Illustration of Vref(DC) tolerance and Vrefac-noise limits
Voltage
VDD
Vref(D
C)
Vref ac-noise
Vref(t)
Vref(DC)
max
Vref(DC)
min
VSS
time
Integrated Silicon Solution, Inc. www.issi.com
31
Rev. J
03/14/2016

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