IS43TR16640A-15GBLI View Datasheet(PDF) - Unspecified

Part Name

Description

Manufacturer

IS43TR16640A-15GBLI

128MX8, 64MX16 1Gb DDR3 SDRAM

Unspecified 

IS43/46TR16640A, IS43/46TR16640AL

IS43/46TR81280A, IS43/46TR81280AL

26. tCL(abs) is the absolute instantaneous clock low pulse width, as measured from one falling edge to the following

rising edge.

27. The tIS(base) AC150 specifications are adjusted from the tIS(base) specification by adding an additional 100ps of

derating to accommodate for the lower altemate threshold of 150mV and another 25ps to account for the earlier

reference point [(175mV - 150mV) / 1V/ns].

28. Pulse width of a input signal is defined as the width between the first crossing of Vref(dc) and the consecutive

crossing of Vref(dc).

29. tDQSL describes the instantaneous differential input low pulse width on DQS - DQS#, as measured from one falling

edge to the next consecutive rising edge.

30. tDQSH describes the instantaneous differential input high pulse width on DQS - DQS#, as measured from one rising

edge to the next consecutive falling edge.

31. tDQSH,act + tDQSL,act = 1 tCK,act ; with tXYZ,act being the actual measured value of the respective timing

parameter in the application.

32. tDSH,act + tDSS,act = 1 tCK,act ; with tXYZ,act being the actual measured value of the respective timing parameter

in the application.

Integrated Silicon Solution, Inc. – www.issi.com –

71

Rev. J

03/14/2016

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