DS3508E View Datasheet(PDF) - Maxim Integrated
Part Name
Description
Manufacturer
DS3508E Datasheet PDF : 14 Pages
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I2C, 8-Channel Gamma Buffer with EEPROM
PIN
1
2
3
4
5
6
7
8
9
10, 11
12
13
14
15
16
17
18
19
20
NAME
SCL
SDA
GND
A0
VHH
VHM
VLM
VLL
VDD
N.C.
GM8
GM7
GM6
GM5
GM4
GM3
GM2
GM1
VCC
Pin Description
TYPE
Input
Input/
Output
FUNCTION
Serial Clock Input. I2C clock input.
Serial Data Input/Output (Open Drain). I2C bidirectional data pin that requires a pullup
resistor to realize high logic levels.
Ground
Input
Ground
Address Input. Determines I2C slave address.
Reference
High-Voltage DAC, Upper Reference
Input
Reference
High-Voltage DAC, Lower Reference
Input
Reference
Low-Voltage DAC, Upper Reference
Input
Reference
Low-Voltage DAC, Lower Reference
Input
Power
—
Analog Supply
No Connection
Output
Gamma Analog Outputs 5–8. These pins are the low-voltage gamma outputs
referenced to VLL and VLM.
Output
Gamma Analog Outputs 1–4. These pins are the high-voltage gamma outputs
referenced to VHH and VHM.
Power Digital Supply
Detailed Description
The DS3508 provides eight independent DACs that
allow precise and repeatable setting of gamma curves.
The DS3508 provides four high-voltage DACs
(GM1–GM4) that operate between VHH and VHM and
four low-voltage DACs (GM5–GM8) that operate
between VLM and VLL. Each of the DACs provides 8
bits of resolution.
The DS3508 DAC output voltages are independently
controlled by the data stored in that channel’s SRAM
register. The MODE bit in the volatile control register
(CR bit 7) determines how I2C data is written to the
SRAM and EEPROM gamma data registers. Reading
and writing to the SRAM/EEPROM gamma data regis-
ters is based on the state of the MODE bit as follows:
MODE = 0: I2C writes to memory addresses
00h–07h write to both SRAM 1–8 and
EEPROM 1–8.
I2C reads from addresses 00h–07h
read from SRAM 1–8.
MODE = 1: I2C writes to addresses 00h–07h write
to SRAM 1–8.
I2C reads from addresses 00h–07h
read from SRAM 1–8.
Regardless of the MODE bit setting, all I2C reads of
address 00–07h return the contents of the SRAM regis-
ters. Setting MODE = 1 allows for quick writing of SRAM
without the added delay of writing to the associated
EEPROM register. The data that is stored in EEPROM and
SRAM remains unchanged if the MODE bit is toggled.
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