ST72141K
RESET MANAGER (Cont’d)
Internal Low Voltage Detection RESET (option)
Two different RESET sequences caused by the in-
ternal LVD circuitry can be distinguished:
- LVD Power-On RESET
- Voltage Drop RESET
Figure 13. LVD RESET Sequences
VDDnominal
VLVDr
VDD
In the second sequence, a “delay” phase is used
to keep the device in RESET state until VDD rises
up to VLVDr (see Figure 13).
VDD
VDDnominal
VLVDr
VLVDf
RUN
POW ER-
OFF
RESET
INTERNAL RESET FETCH
4096 CLOCK CYCLES VECTOR
RUN
EXTERNAL RESET SOURCE
RESET PIN
WATCHDOG RESET
DELAY
RESET
INTERNAL RESET FETCH
4096 CLOCK CYCLES VECTOR
RUN
EXTERNAL RESET SOURCE
RESET PIN
WATCHDOG RESET
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