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TDA9144 View Datasheet(PDF) - Philips Electronics

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Description
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TDA9144 Datasheet PDF : 44 Pages
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Philips Semiconductors
I2C-bus controlled, alignment-free PAL/NTSC/SECAM
decoder/sync processor with PALplus helper demodulator
Preliminary specification
TDA9144
In case of a PALplus input signal, the standard
identification system of the TDA9144 only determines PAL
and needs additional I2C-bus information for PALplus, via
bus bits MACP, HD, HOB and HBC.
Bus bit MACP determines whether the 4.43 chrominance
signal component of the CVBS input signal should be
suppressed by a 4.43 trap or not. For MACP = 1 the
chrominance suppression takes place outside the
TDA9144.
The HD bit (helper demodulation) enables PALplus helper
demodulation on the U phase (i.e. the BY demodulation
axis). As there is only a 4.43 notch for the demodulated
helper, an external notch filter is necessary to suppress the
8.86 MHz demodulation product and resolve the
baseband helper signal. The demodulated helper
luminance signal is always led to a notch filter (4.43 MHz,
no bypass here), then multiplexed with the regular 430
letter box lines luminance signal and led to the output Yout.
The black level of the luminance signal is internally
clamped with a large time constant to the black level
generated by the helper demodulator.
Also bus bits HD and MACP determine the presence of a
black set-up voltage (with luminance scaling of a factor
0.8) and a helper set-up voltage for the demodulated
helper signal on the output signal Yout. These set-up
voltages are necessary for PALplus signal post processing
outside the TDA9144. The set-up voltages are also
multiplexed into a reference line 22, combined with the
demodulated helper reference of line 23 and luminance
reference of line 623, both present in every PALplus signal
for correct PALplus reference post processing (see Fig.5).
Additional helper blanking bits (HOB, HBC) determine
whether the helper signal has to be blanked or blanked
conditionally depending on the signal-to-noise ratio bit
SNR. Helper blanking can only take place on a norm sync
signal, indicated by output bit NRM = 1. Table 1 is valid in
50 Hz or 60 Hz mode.
Table 1 Helper blanking modes
HOB
0
1
1
1
HBC
X
0
1
1
SNR
X
X
0
1
HELPER
BLANKING
OFF
ON
OFF
ON
For EDTV-2 (system M, 60 Hz, 525 lines) outside the letter
box area, blanking is possible and takes place on lines
230 to 312 and 493 to 49(1) when helper blanking is
activated.
The TDA9144 can handle PALplus signals in either CVBS
or Y/C format. In case of a Y/C signal, the modulated
helper must be available on the chrominance input pin (C).
The use of the 4.43 trap will not be necessary, as the
chrominance and luminance components of a Y/C signal
are already separated, so the 4.43 trap for the letter box
luminance is bypassed (not for the demodulated helper
signal). During helper demodulation, the internal chroma
bandpass filter is bypassed.
For PALplus the I2C-bus Hue bits HU0 to HU5 are used to
adjust for a correct helper demodulator phase. This has no
effect on the RY and BY demodulator phase for PAL.
Table 2 gives an overview of the possible PALplus modes
and their effects in the TDA9144. The table is only valid for
a 50 Hz system. In 60 Hz system mode the columns for
line 22, 23b and 623a do not exist, and using the MACP
and HD bits has no effect on the 60 Hz signal.
Mode 1 normal PAL
Mode 2 PAL with MACP processing
Mode 3 full PALplus
Mode 4 PALplus without MACP processing (helper
only)
Mode 5 near_norm or no_norm sync condition
Mode 6 norm sync condition with fast blanking active
Mode 7 system ident not identified as PAL.
The indications a and b for the lines 22, 23 and 623
respectively stand for the first half and the second half of a
line.
The signalling bits in line 23 (see Fig.5) are processed in
the same manner as letter box luminance lines in the
TDA9144. Signalling bit decoding and PALplus
identification is done externally with I2C-bus as
communication link to the TDA9144 for bus bits MACP,
HD, HOB, and HBC.
(1) For system M the line numbers start with the first equalizing
pulse in field 1, but the internal line counter starts counting at
the first vertical sync pulse in field 1. This line number
notation is used here and in Fig.9.
1996 Jan 17
9

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