TDA9143 View Datasheet(PDF) - Philips Electronics

Part Name

Description

Manufacturer

TDA9143

I2C-bus controlled, alignment-free PAL/NTSC/SECAM decoder/sync processor

Philips Electronics 

Philips Semiconductors

I2C-bus controlled, alignment-free

PAL/NTSC/SECAM decoder/sync processor

Preliminary specification

TDA9143

The divider system operates at twice the horizontal

frequency. The line counter receives enable pulses at this

frequency, thereby counting two pulses per line. A state

diagram of the controller is shown in Fig.5. Because it is

symmetrical only the right-hand part will be described.

Depending on the previously found vertical frequency, the

controller will be in one of the COUNT states. When the

line counter has counted 488 pulses (i.e. 244 lines of the

video input signal), the controller will move to the next state

depending on the output of the norm counter. This can be

either NORM, NEAR_NORM or NO_NORM, depending

on the position of the vertical sync pulse in the previous

fields. When the controller is in the NORM state it

generates the vertical sync pulse (VSP) automatically and

then, when the line counter is at LC = 626, moves to the

WAIT state. In this condition it waits for the next pulse of

the double line frequency signal, and then moves to the

COUNT state of the current field frequency. When the

controller returns to the COUNT state, the line counter will

be reset half a line after the start of the vertical sync pulse

of the video input signal. The NORM window normally

looks within one line width and a sudden half line delay of

the vertical sync pulse change can therefore be neglected.

handbook, full pagewidth

no_norm

else

NO

NORM

no_norm

LC = 528 or LC = 576 or on VSP LC = 628 or LC = 722 or on VSP

LC < 488

COUNT

on SYNC

if LC < 576

norm

LC = 526

WAIT

FOR

RESET

PULSE

on SYNC

if LC ≥ 576

LC < 488

COUNT

LC = 626

norm

near_norm

NORM

LC ≤ 525

NORM

LC ≤ 625

near_norm

on VSP if

522 < LC < 528

or on LC = 528

NEAR

NORM

NEAR

NORM

on VSP if

622 < LC < 628

or on LC = 628

LC < 522

vertical frequency 60 Hz

LC < 622

vertical frequency 50 Hz

MGE042

1996 Jan 17

Fig.5 State diagram of the vertical divider system.

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