TDA9143/N1 View Datasheet(PDF) - Philips Electronics

Part Name

Description

Manufacturer

TDA9143/N1

I2C-bus controlled, alignment-free PAL/NTSC/SECAM decoder/sync processor

Philips Electronics 

Philips Semiconductors

I2C-bus controlled, alignment-free

PAL/NTSC/SECAM decoder/sync processor

Preliminary specification

TDA9143

If the reference crystal is not 4.4 MHz the decoder will not

produce the correct SECAM signals. Especially for NTSC

applications an internal bypass mode of the external

baseband delay line (for instance TDA4665) is added,

controlled by bus bit BPS (bypass mode) and with a gain

of 2. The bypass mode is not available for SECAM.

Comb filter interfacing

The frequency of the active crystal is fed to the Fscomb

output, which can be connected to an external comb filter

IC (e.g. SAA4961). When bus bit ECMB is LOW, the

subcarrier frequency is suppressed and its DC value is

LOW. With ECMB HIGH, the DC value is HIGH with the

subcarrier frequency present, and I2C-bus output bit YC

and the input switch are always forced in the Y/C mode,

unless an external current sink (e.g. from the comb filter)

prevents this, as pin Fscomb also acts as input pin. In this

event the subcarrier frequency is still present on the same

DC HIGH level.

PALplus and EDTV-2 helper blanking

For blanking of PALplus or EDTV-2 helper lines, the helper

blanking can extend the vertical blanking of the Y, R−Y and

B−Y outputs. Additional helper blanking bits (HOB, HBC)

and norm/not norm (NRM) indication determine whether

the helper signal has to be blanked or conditionally

blanked depending on the signal-to-noise ratio bit SNR.

Table 1 is valid in a 50 Hz or 60 Hz mode.

Table 1 Helper blanking modes

HOB

0

1

1

1

HBC

X

0

1

1

SNR

X

X

0

1

HELPER

BLANKING

OFF

ON

OFF

ON

For PALplus (50 Hz, 625 lines) outside the letter box area

blanking is possible and takes place on lines 275 to 371

and 587 to 59.

For EDTV-2 (system M, 60 Hz, 525 lines) outside the letter

box area blanking is possible and takes place on lines 230

to 312 and 493 to 49 (1).

(1) For system M, line numbers start with the first equalizing

pulse in field 1, but the internal line counter starts counting at

the first vertical sync pulse in field 1. This line number

notation is used here and in Fig.7.

Provided a NORM sync condition is present, with bus bit

HBO = 1 and HBC = 0 blanking is activated. Conditional

blanking is possible with HBO = 1 and HBC = 1 and

SNR = 1.

The black level of the luminance signal is internally

clamped with a large time constant to an internal reference

black level. This black level is used as fill-in value for the Y

signal during blanking.

Fast blanking detector

To detect the presence of a fast blanking signal, a circuit is

added which indicates this event if in more than one line

per field a blanking pulse is present at the fast blanking

input (F). More than one line per field is chosen to prevent

switching-off at every spike detected on the fast blanking

input. The detector output FBA (fast blanking active) can

be read-out by the I2C-bus.

Blanked/unblanked sync

By means of the I2C-bus bit BSY (blanked sync) output

signal Yout will be presented with or without its composite

sync part. At BSY = 0 the composite sync is present on

Yout. When activated, helper blanking takes place only

during helper lines scan. At BSY = 1 the black level is filled

in during the line blanking interval and vertical blanking

interval. When activated, the helper blanking extends the

vertical blanking.

Sync processor (ϕ1 loop)

The main part of the sync circuit is an oscillator running at

440 × fH (6.875 MHz), provided that I2C-bus address 8A is

used or 432 × fH (6.75 MHz) for 8E. Its frequency is divided

by 440 or 432 to lock the ϕ1 loop to the incoming signal.

The time-constant of the loop can be selected by the

I2C-bus (fast, auto or slow). In the fast mode the fast

time-constant is chosen independent of signal conditions.

In the auto mode the medium time-constant is present with

a fast time constant during the vertical retrace period (‘field

boost’). If the noise detector indicates a noisy video signal

the time-constant switches to slow with a smaller field

boost, which is also the time-constant for the slow mode.

In case of a slow time constant sync gating takes place in

a 6 µs window around the separated sync pulse. In case of

no sync lock, both the auto and the slow mode have a

medium time constant, to ensure reliable catching.

The noise content of the video signal is determined by a

noise detector circuit. This circuit measures the noise at

top sync during a 15 line period every field (65 lines after

start VA pulse). When the noise level supersedes the

1996 Jan 17

8

Share Link: