AA104SH02 View Datasheet(PDF) - Unspecified

Part Name

Description

Manufacturer

AA104SH02

10.4” SVGA

Unspecified 

6. INTERFACE TIMING

LVDS transmitter input signal

(1) Timing Specifications

ITEM

SYMBOL MIN.

TYP.

MAX.

UNIT

Frequency

DCLK Period

fCLK

35

40

42

MHz

tCLK

23.8

25

28.6

ns

Active Time

tHA

800

800

800

tCLK

Blanking Time

tHB

20

256

--

tCLK

Horizontal

Frequency

fH

35.2

37.9

39.2

kHz

DENA

Period

tH

25.5

26.4

28.4

μs

Active Time

tVA

600

600

600

tH

Blanking Time

tVB

3

Vertical

Frequency

fV

55

28

--

tH

60

64.2

Hz

Period

tV

15.6

16.7

18.2

ms

[Note]

1) DENA (Data Enable) should always be positive polarity as shown in the timing specification.

2) DCLK should appear during all invalid period.

3) LVDS timing follows the timing specifications of LVDS receiver IC: THC63LVDF84B(Thine).

4) In case of blanking time fluctuation, please use following.

tVBn > tVBn-1 − 3(tH)

MITSUBISHI

(9/24)

AA104SH02_02_00

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