MTP805N View Datasheet(PDF) - Unspecified

Part Name

Description

Manufacturer

MTP805N

8051 Embedded USB/PS2 Keyboard/Mouse Controller

Unspecified 

MYSON

TECHNOLOGY

MTP805

(Rev. 0.9)

RsmIE = 1

KbdIE = 1

MsIE = 1

→ Enable RsmI interrupt.

→ Enable KbdI interrupt.

→ Enable MsI interrupt.

USBCTR (r/w) : USB control register.

Susp = 1 → S/W force USB interface into suspend mode.

RsmO = 1 → S/W force USB interface send RESUME signal in suspend mode.

EP1cfgd = 1 → Endpoint 1 is configed.

EP2cfgd = 1 → Endpoint 2 is configed.

RC0rdy = 1 → Enable the Endpoint 0 to respond to OUT token.

= 0 → Endpoint 0 will respond NAK to OUT token.

This bit can be set or cleared by S/W, clear by H/W while RC0I occurs.

CtrRD = 1 → MTP805 will stall an invalid OUT token during Control Read transfer.

EP0STUS (r) : Endpoint 0 status.

RC0tgl = 1 → Receive a DATA1 packet.

= 0 → Receive a DATA0 packet.

RC0err = 1 → Receive DATA packet error.

= 0 → Receive DATA packet good.

EP0dir = 1 → Last transfer is transmit direction (IN).

= 0 → Last transfer is receive direction (OUT, SETUP).

EP0set = 1 → Last transfer is a SETUP.

= 0 → Last transfer is not a SETUP.

RC0cnt :

Last transfer's receive byte count.

TX0CTR (r/w) : Endpoint 0 transmit control register.

TX0rdy = 1 → Enable the Endpoint 0 to respond to IN token.

= 0 → Endpoint 0 will respond NAK to IN token.

This bit can be set or cleared by S/W, clear by H/W while Host ack the transfer.

TX0tgl = 1 → Endpoint 0 will transmit DATA1 packet.

= 0 → Endpoint 0 will transmit DATA0 packet.

EP0stall = 1 → Endpoint 0 will stall OUT/IN packet.

TX0cnt (w) : Endpoint 0 transmit byte count, write only.

TX1CTR (r/w) : Endpoint 1 transmit control register.

TX1rdy = 1 → Enable the Endpoint 1 to respond to IN token.

= 0 → Endpoint 1 will respond NAK to IN token.

This bit can be set or cleared by S/W, clear by H/W while Host ack the transfer.

TX1tgl = 1 → Endpoint 1 will transmit DATA1 packet.

= 0 → Endpoint 1 will transmit DATA0 packet.

EP1stall = 1 → Endpoint 1 will stall IN packet.

TX1cnt (w) : Endpoint 1 transmit byte count, write only.

TX2CTR (r/w) : Endpoint 1 transmit control register.

TX2rdy = 1 → Enable the Endpoint 2 to respond to IN token.

= 0 → Endpoint 2 will respond NAK to IN token.

This bit can be set or cleared by S/W, clear by H/W while Host ack the transfer.

TX2tgl = 1 → Endpoint 2 will transmit DATA1 packet.

= 0 → Endpoint 2 will transmit DATA0 packet.

EP2stall = 1 → Endpoint 2 will stall IN packet.

TX2cnt (w) : Endpoint 1 transmit byte count, write only.

KSI (r) :

KSI7~0’s read result.

LED (w) :

Data load into the GPO0 / LED2~0 output latch.

Revision 0.9

- 11 -

2000/07/19

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