MTP805N View Datasheet(PDF) - Unspecified

Part Name

Description

Manufacturer

MTP805N

8051 Embedded USB/PS2 Keyboard/Mouse Controller

Unspecified 

MYSON

TECHNOLOGY

MTP805

(Rev. 0.9)

4. USB and PS2 Mode Detection

After reset, the USB transceiver is disable, and the V33 pin is in high impedance state (no 3.3 volt output).

S/W can detect the application is USB mode or PS2 mode by reading P3.4/P3.5. At first, S/W can set

“PS2KB”=1. This control bit is used to enable the internal 250K pull-up resistor on DP/DM pin. If the chip is

connected to USB Hub, the P3.4/P3.5 is 0 because of the 15K pull-down resistor on Hub. Otherwise,

P3.4/P3.5 is 1.

5. Power-down and Idle Mode

The Power-down/Idle mode is activated by S/W setting the PD/IDL bit in 8051’s PCON register. In Power-

down mode, the MTP805’s X’tal stop oscillating. In Idle mode, the 8051’s instruction clock is stop. The

Power-down/Idle mode is released by any enable interrupt. For standard 8051, Power-down mode is

released only by chip reset.

6. Watch-Dog-Timer(WDT) and Low-Voltage-Reset(LVR)

The WDT is enable by setting the “WDTen” bit in XFR. The time out period is 0.64 second. S/W can clear

WDT by writing the WDT register.

The LVR can generate chip reset when VDD is below 3.0 volt, including both power-on and power-off

process.

7. Fast Clock Option

The CPU can run at double clock rate when S/W setting the “FCLKen” bit in XFR. Once setting, the 8051 is

running at the rate as if a 12MHz X’tal is on OSC pins. However, S/W must clear the FCLKen bit before

entering Power-down mode.

8. USB Engine

The USB engine includes the Serial Interface Engine (SIE), the low-speed USB I/O transceiver and the 3.3

Volt Regulator. The SIE block performs most of the USB interface function with only minimum support from

S/W. Three endpoints are supported. Endpoint 0 is used to receive and transmit control (including SETUP)

packets while Endpoint 1 and endpoint 2 are only used to transmit data packets.

The USB SIE handles the following USB bus activity independently:

1. Bitstuffing/unstuffing

2. CRC generation/checking

3. ACK/NAK

4. TOKEN type identification

5. Address checking

S/W handles the following tasks:

1. Coordinate enumeration by responding to SETUP packets

2. Fill and empty the FIFOs

3. Suspend/Resume coordination

4. Verify and select DATA toggle values

8.1 USB Device Address

The USBADR register stores the device address. This register is reset to all 0 after chip reset or USB bus

reset. S/W must write this register a valid value after the USB enumeration process.

8.2 Endpoint 0 receive

After receiving a packet and placing the data into the Endpoint 0 receive FIFO (RC0FIFO), MTP805 updates

the Endpoint 0 status register (EP0STUS) to record the receive status and then generates an Endpoint 0

Revision 0.9

-7-

2000/07/19

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