MTP805N View Datasheet(PDF) - Unspecified

Part Name

Description

Manufacturer

MTP805N

8051 Embedded USB/PS2 Keyboard/Mouse Controller

Unspecified 

MYSON

TECHNOLOGY

MTP805

(Rev. 0.9)

receive interrupt (RC0I). S/W can read the EP0STUS register for the recent transfer information, which

includes the data byte count (RC0cnt), data direction (EP0dir), SETUP token flag (EP0set) and data valid

flag (RC0err). The received data is always stored into RC0FIFO and the RC0cnt is always updated for DATA

packets following SETUP tokens. The data following an OUT token is written into the RC0FIFO, and the

RC0cnt is updated unless Endpoint 0 STALL (EP0stall) is set or Endpoint 0 receive ready (RC0rdy) is

cleared. The SIE clears the RC0rdy automatically and generates RC0I interrupt when the RC0cnt/RC0FIFO

is updated. As long as the RC0rdy is cleared, SIE keep responding NAK to Host’s Endpoint 0 OUT packet

request. S/W should set the RC0rdy flag after the RC0I interrupt is asserted and RC0FIFO is read out.

8.3 Endpoint 0 transmit

After detecting a valid Endpoint 0 IN token, MTP805 automatically transmit the data pre-stored in the

Endpoint 0 transmit FIFO (TX0FIFO) to the USB bus if the Endpoint 0 transmit ready flag (TX0rdy) is set and

the EP0stall is cleared. The number of byte to be transmitted is base on the Endpoint 0 transmit byte count

register (TX0cnt). The DATA0/1 token to be transmitted is base on the Endpoint 0 transmit toggle control bit

(TX0tgl). After the TX0FIFO is updated, TX0rdy should be set to 1. This enables the MTP805 to respond to

an Endpoint 0 IN packet. TX0rdy is cleared and an Endpoint 0 transmit interrupt (TX0I) is generated once the

USB host acknowledges the data transmission. The interrupt service routine can check TX0rdy to confirm

that the data transfer was successful.

8.4 Endpoint 1/2 transmit

Endpoint1 and Endpoint2 are capable of transmit only. These endpoints are enable when the Endpoint1/

Endpoint2 configured control bit (EP1cfgd/EP2cfgd) is set. After detecting a valid Endpoint 1/2 IN token,

MTP805 automatically transmit the data pre-stored in the Endpoint 1/2 transmit FIFO (TX1FIFO/TX2FIFO) to

the USB bus if the Endpoint 1/2 transmit ready flag (TX1rdy/TX2rdy) is set and the EP1stall/EP2stall is

cleared. The number of byte to be transmitted is base on the Endpoint 1/2 transmit byte count register

(TX1cnt/TX2cnt). The DATA0/1 token to be transmitted is base on the Endpoint 1/2 transmit toggle control

bit (TX1tgl/TX2tgl). After the TX1FIFO/TX2FIFO is updated, TX1rdy/TX2rdy should be set to 1. This enables

the MTP805 to respond to an Endpoint 1/2 IN packet. TX1rdy/TX2rdy is cleared and an Endpoint 1/2

transmit interrupt (TX1I/TXI2) is generated once the USB host acknowledges the data transmission. The

interrupt service routine can check TX1rdy/TX2rdy to confirm that the data transfer was successful.

8.5 USB Control and Status

Other USB control bits include the USB enable (ENUSB), SUSPEND (Susp), RESUME (RsmO), Control

Read (CtrRD), and corresponding interrupt enable bits. The CtrRD should be set when program detects the

current transfer is an Endpoint0 Control Read Transfer. Once this bit is set, the MTP805 will stall an

Endpoint0 OUT packet with DATA toggle 0 or byte count other than 0. Other USB status flag includes the

USB reset interrupt (RstI), RESUME interrupt (RsmI), and USB Suspend interrupt (SusI).

8.6 Suspend and Resume

Once the Suspend condition is asserted, S/W can set the Susp bit to stop the USBSIE's clock. In the mean

time, the 3.3V Regulator is operating in low power mode. S/W can further save the device power by force the

8051 CPU core into the Power Down or Idle mode by setting the PCON register in SFR area. In the Idel

mode, the X'tal keeps oscillating and CPU can be waken-up by the trigger of any enabled interrupt. In the

Power Down mode, the X'tal is stop, but CPU can be waken-up by the trigger of enabled interrupt's source.

In short, S/W can keep the RsmI/KbdI/MsI alive before enter the suspend mode.

The MTP805 send Resume signaling to USB bus when Susp=1 and RSMO=1. In the suspend mode, if a

keyboard or mouse interrupt is asserted, S/W should send resume signal to wake up the USB bus.

Revision 0.9

-8-

2000/07/19

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