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UPD61P34BGS View Datasheet(PDF) - NEC => Renesas Technology

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Description
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UPD61P34BGS Datasheet PDF : 207 Pages
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LIST OF FIGURES (2/2)
Figure No.
Title
Page
3-1
Timing Chart when Key is Pressed and Held .................................................................................. 108
3-2
Timing Chart for Key OFF Status ..................................................................................................... 109
3-3
Output Patterns Prior to Key Confirmation ...................................................................................... 112
3-4
Timing Chart of Key Combination Operation ................................................................................... 118
3-5
Operation Timing of Key Transfer Operation ................................................................................... 120
5-1
5-2
5-3
6-1
6-2
6-3
6-4
6-5
6-6
6-7
6-8
6-9
6-10
6-11
6-12
General Flow Chart ........................................................................................................................... 123
ROM Map .......................................................................................................................................... 124
Data Table Map ................................................................................................................................. 125
Chattering of Key Input Signal ......................................................................................................... 139
Key ON Judgment when Chattering Occurs .................................................................................... 140
80-key Key Matrix ............................................................................................................................. 141
Key Matrix .......................................................................................................................................... 142
Key Data (Key Position) ................................................................................................................... 142
Bit Configuration of Key Data when Input is via KI0 to KI3 .............................................................. 143
Bit Configuration of Key Data when Input is via S1 ......................................................................... 144
Configuration of Data Pointer ........................................................................................................... 144
Configuration of Timer Counter ........................................................................................................ 158
Time Management of Timer Counter ............................................................................................... 158
Method for Dividing Frame Space Transmission Times .................................................................. 162
Key OFF Check during Bit Data Transmission ................................................................................ 163
–v–

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