CS7615-KQ View Datasheet(PDF) - Cirrus Logic

Part Name

Description

Manufacturer

CS7615-KQ

CCD Imager Analog Processor

Cirrus Logic 

CS7615

The EAV/SAV code definitions are consistent with

an 8-bit data path. As per the ITU-656 recommen-

dation, the LSB’s of the CS7615 are fractional bits

which are not used when delivering 8-bit output da-

ta. In 10-bit mode, all ten digital outputs can be

connected directly to the CS7665.

The output data format from the CS7615 formatter

is shown in Figure 6. The CS7615 also outputs two

clocks, one at the pixel rate and the other at 2× the

HREF

Blanking period

output pixel data rate (see pin description for

CLK2XO). The output of the formatter is avail-

able at the pins DO[0..9] and it transitions at the fall-

ing edge of the pixel rate clock CLKO. Figure 7

shows the basic output timing diagram. The falling

edges of CLKO lag the falling edges of CLK2XO

by 4 to 8 ns and both clocks have approximately

50% duty cycles.

Active video

4T

NbT

4T

AV*T

T = output pixel period

EAV code (10 bits)

Smpl.

Word

0

3FFh

1

000h

2

000h

Binary

3

1fv1P3P2P1P000

Blank code (10 bits)

Smpl.

Word

4

040h

repeat above word

During active video,

samples of mosaic data;

during vertical blanking,

040h.

At reset or power down, 040h.

SAV code (10 bits)

Smpl.

Word

0

3FFh

1

000h

2

000h

Binary

3

1fv0P3P2P1P000

f = field bit; 0 (odd field), 1 (even field)

v = vertical blanking bit; 0 (active video lines), 1(vertical blanking)

P3P2P1P0 = error protection bits (as per ITU-656).

Figure 6. CS7615 Output Data Format

DS231PP6

7

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