TB62718AFG View Datasheet(PDF) - Marktech Optoelectronics
Part Name
Description
Manufacturer
TB62718AFG Datasheet PDF : 31 Pages
| |||
TB62718AFG
Explanation of Pin Functions Table
No.
Name
I/O
Function Explanation
4, 45
VSS
P ⎯ Logic ground pins. Be sure to use all.
35, 14
NC
⎯ ⎯ Unused
This pin is used to reset the IC’s built-in temperature monitoring circuit (TSD).
63
TSENA
I
Pull- Rising edge of input signal re-enables outputs which had been forced to OFF.
up The latched data as the setting is not reset.
Either in case of H- or L-level of this terminals can be operated TSD circuit.
15, 24,
25, 34
VSS2
P ⎯ Ground pin for output. Be sure to use all.
13, 36
VDD
P ⎯ Logic power supply input pins. Be sure to use all.
16~23, OUT 00~
26~33 OUT 15
O ⎯ LED drive output pins. Connect to cathode of LED.
50
SI DATA
I
⎯
Serial data input pin. Used for input of standard current adjustment data and dot
adjustment data
51
SI CLK
I
⎯ Serial data transfer clock input pin. Data is transferred positive edge.
52
SI LATCH
I
Pull-
down
Serial data latch signal input pin. Data is held on positive edge.
53
SI SEL
I
⎯
Serial data selection pin. Either standard current adjustment data or dot adjustment data
may be selected.
62
SO DATA
O ⎯ Serial data output pin. The output data type is selected using SI SEL.
37~44
PI DATA 00~
PI DATA 07
I
Pull-
down
Input pins for parallel data. Inputs for all output adjustment data and PWM data
46
PI CLK
I
⎯ Input pin for parallel data transfer clock. Data is transferred on positive edge.
47
PI LATCH
I
Pull-
down
Input pin for parallel data latch signal. Data is held on rising positive edge.
48
PI SEL
I
⎯
Parallel data selection pin. Either all output adjustment data or PWM data may be
selected.
5~12
PO DATA 00~
PO DATA 07
O
⎯ Output pin for parallel data. The output data type is selected using PISEL.
49
DOE
I
⎯
Control pin for parallel data output PODATA. PIDATA is out on input of an H-level signal.
PIDATA is set to High-impedance by input of an L-level signal.
59
BLANK
I
Pull- PWM circuit control signal input pin. Output is turn OFF by input of an H-level signal. PWM
up output is initiated by input of an L-level signal accordingly to the input data.
54
PWMCLK
I
⎯
Standard clock input pin for PWM circuit. One clock cycle is equivalent to the minimum
pulse width of the PWM output.
55
BCEN
I
Pull-
up
Selection signal input pin for all output adjustment functions. All output adjustment is fixed
to 100% when this signal is Low. All bit adjustments become effective when it is High.
It isn’t influent anything to all output adjustment by PWMCLK.
56
DCEN
I
Pull- Selection signal input pin for dot adjustment function. Dot adjustment value is fixed to
up 100% when this signal is Low. Dot adjustment becomes effective when it is High.
57
RESET
I
⎯
Reset signal input pin. Setting and registered data are reset when it is Low.
A reset also releases TSD.
58
LED TEST
I
Pull-
down
Connection confirmation signal input pin for an LED. When this signal is High, all outputs
are ON.
This signal should normally be kept Low.
60
REXT
P ⎯ Connection pin of resistor for setting for the current.
Open-drain monitor pin for TSD circuit. When the TSD circuit detects an abnormal
2
ALARM1
O ⎯ temperature, this signal is turned ON. IO monitor the TSD circuit connect this pin to a
pull-up resistor. ALARM1 is independent of the RESET signal.
3
ALARM2
O
⎯
Open-drain monitor pin for output-open detection circuit. When an open output is detected,
this signal is turned ON.
1, 64
TEST 0,
TEST 1
I
⎯ Pins for the device testing. Connect all these pins to ground.
Pin attributes P: power supply/ground/other, I: input pin, O: output pin
Note 3: It is recommended that pins with pull-up or pull-down resistors not be left open.
Ambient noise may cause malfunction of the device.
7
2005-04-20
Share Link: 