MPC2605ZP66R View Datasheet(PDF) - Motorola => Freescale
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MPC2605ZP66R Datasheet PDF : 30 Pages
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FUNCTIONAL OPERATION
SYSTEM USAGE AND REQUIREMENTS
The MPC2605 is a high–performance look–aside cache
for PowerPC systems. A look–aside cache is defined as a
cache that resides on the same bus as the processor, the
memory controller, the DMA bridge, and the arbiter. The ad-
vantage of a look–aside cache is that, when the processor
makes a memory request, the cache adds no delay to the
memory controller’s response time in the event that the re-
quest cannot be satisfied by the cache. However, there are
certain system requirements that must be met before a look–
aside cache can be used.
Comprehension of L2 CLAIM
Because the memory controller sees every memory re-
quest that is issued by the processor, there must be a mech-
anism for the cache to inform the memory controller that it
has detected a cache hit and that it will satisfy the proces-
sor’s request. The MPC2605 has a signal called
L2 CLAIM that is asserted whenever a cache hit is detected.
Any memory controller with which the MPC2605 is to be
used must have the ability to monitor this signal.
Pipeline Depth
The 60X bus allows pipelining of transactions such that a
new transaction can be initiated before a previous transac-
tion has fully completed. The level of pipelining that exists on
the bus is defined by how many new data transactions have
been initiated while the original transaction is still being pro-
cessed. By this definition the MPC2605 can only work in a
one level deep pipeline. In the presence of transactions for
which it has asserted L2 CLAIM, the MPC2605 can control
the level of pipelining by delaying its assertion of AACK.
However, for transactions that it cannot control, the
MPC2605 is dependent upon the memory controller to con-
trol pipeline depth. Thus, another system requirement for the
use of the MPC2605 is the use of a memory controller that
only allows one level deep of pipelining on the 60X bus.
Bus Mastering
Bus mastering is a requirement only for systems which
seek to use the MPC2605 as a copyback, as opposed to a
write–through, cache. The requirement is that the system ar-
biter must have the ability to allow the MPC2605 to become
a bus master. Specifically, the system arbiter must be able to
recognize assertions of L2 BR and must have the ability to
assert L2 BG and L2 DBG.
These are the only requirements above and beyond what
should already exist in a PowerPC system. All other neces-
sary control signals are signals that are required for the pro-
cessor to communicate with the memory controller, the DMA
bridge, and the arbiter.
CONFIGURATION PINS
The MPC2605 has five configuration pins: CFG0, CFG1,
CFG2, CFG3, and CFG4.
CFG0 – CFG2
These three configuration pins are used to implement the
different cache sizes supported by the MPC2605.
256KB: For a single chip implementation, CFG0, CFG1,
and CFG2 should all be tied low.
512KB: This two chip configuration requires both parts to
have CFG0 tied low and CFG1 tied high. CFG2 is
used as a chip select when it matches the value of
A26. Therefore, one device must have CFG2 tied
low and the other device must have CFG2 tied
high.
1MB:
The four chip configuration requires all four de-
vices to have CFG0 tied high. The CFG1, CFG2
vector becomes the chip select when it matches
the A25, A26 vector. Therefore, each of the four
parts must have a unique value of the CFG[1:2]
vector.
CFG3
Many core logic chipsets are designed such that the DMA
bridge and the memory controller are resident in the same
device. In such systems there is internal communication be-
tween these two functional units. Bus transactions generated
by the DMA bridge are solely for the purpose of keeping the
system coherent. They are not explicit requests from
memory that have data tenures associated with them. How-
ever, some chipsets are designed with the memory controller
and the DMA bridge partitioned into different devices. In sys-
tems such as these, transactions generated by the DMA
bridge are true memory requests that have data tenures
associated with them. These are called snoop data tenures.
Because these two types of systems are fundamentally dif-
ferent, the MPC2605 must know in which type of system it is
resident in order to respond properly to the different types of
transactions. For systems that do not have snoop data ten-
ures, CFG3 must be tied high. For systems that do use
snoop data tenures, CFG3 must be tied low.
CFG4
When the MPC2605 asserts L2 CLAIM to signal to the
memory controller that a cache hit has been detected, it is
taking control of the address and data tenures of the transac-
tion (see 60X Bus Operation and Memory Coherence).
This means that the MPC2605 will assert AACK to end the
address tenure, and it will assert TA as needed for the data
tenure. If the data bus is idle when a processor request is ini-
tiated, the MPC2605 will assert AACK the cycle after TS was
asserted. If the data bus is busy when the request is made,
the MPC2605 will wait until the outstanding data tenure has
completed before asserting AACK. By holding off on the
assertion of AACK, the MPC2605 enforces the policy of, at
most, two outstanding data transactions at any one time. Ty-
ing CFG4 low prevents the MPC2605 from asserting AACK
to end transactions for which it has asserted L2 CLAIM. In
systems that tie CFG4 low it is necessary for the memory
controller to assert AACK for all transactions. This allows the
DMA bridge to initiate snoop transactions (as defined later)
even when there are two outstanding data transactions. If
this type of system is implemented, the arbiter must ensure
MPC2605
10
MOTOROLA
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