MPC2605ZP66R View Datasheet(PDF) - Motorola => Freescale
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Description
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MPC2605ZP66R Datasheet PDF : 30 Pages
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
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by MPC2605/D
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Integrated Secondary Cache
for PowerPC™ Microprocessors
The MPC2605 is a single chip, 256KB integrated look–aside cache with
copy–back capability designed for PowerPC applications (MPC603 and
MPC604). Using 0.38 µm technology along with standard cell logic technology,
the MPC2605 integrates data, tag, host interface, and least recently used (LRU)
memory with a cache controller to provide a 256KB, 512KB, or 1 MB Level 2
cache with one, two, or four chips on a 64–bit PowerPC bus.
• Single Chip L2 Cache for PowerPC
• 66 MHz Zero Wait State Performance (2–1–1–1 Burst)
• Four–Way Set Associative Cache Design
• 32K x 72 Data Memory Array
• 8K x 18 Tag Array
• Address Parity Support
• LRU Cache Control Logic
• Copy–Back or Write–Through Modes of Operation
• Copy–Back Buffer for Improved Performance
• Single 3.3 V Power Supply
• 5 V Tolerant I/O
• One, Two, or Four Chip Cache Solution (256KB, 512KB, or 1MB)
• Single Clock Operation
• Compliant with IEEE Standard 1149.1 Test Access Port (JTAG)
• Supports up to Four Processors in a Shared Cache Configuration
• High Board Density 25 mm 241 PBGA Package
BLOCK DIAGRAM
COPY–BACK
BUFFER
MPC2605
ZP PACKAGE
PBGA
CASE 1138–01
CONTROL
60X BUS
INTERFACE
A0 – A31
CONTROLLER
AND
BUS INTERFACE
RD/WR
A27, A28
RD/WR
2K x 8 LRU
8K x 72 x 4
DATA RAM
2K x 18 x 4
TAG RAM
WAY SELECT
DH0 – DH31
DL0 – DL31
DP0 – DP7
COMPARE
The PowerPC name is a trademark of IBM Corp., used under license therefrom.
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.
REV 6
2/26/98
©MMOoTtoOrolRa,OIncL.A1998
MPC2605
1
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