MU9C8148-FC View Datasheet(PDF) - Unspecified

Part Name

Description

Manufacturer

MU9C8148-FC

SRT Interface

Unspecified 

MU9C8148

FUNCTIONAL DESCRIPTION (CONT’D)

For a non-arbitrated Write cycle, /HBEN and /HBDIR go LOW

after the second rising edge of RXC past the falling edge of

/WS (Intel mode) or /UDS and /LDS (Motorola mode). /HBRDY

goes LOW after the second rising edge of RXC past the falling

edge of /HBEN for Register and Instruction Buffer write cycles,

and after the 8th rising edge of RXC past the falling edge of

/HBEN for CAM write cycles. The write data on the D(15-0) bus

is strobed by the rising edge of RXC that outputs /HBRDY.

For a non-arbitrated Read cycle, /HBEN goes LOW after the

third rising edge of RXC past the falling edge of /RS (Intel

mode) or /UDS and /LDS (Motorola mode). /HBRDY goes LOW

after the first rising edge of RXC past the falling edge of /HBEN

for a Register read cycle, the 4th rising edge of RXC past the

falling edge of /HBEN for an Instruction Buffer read cycle, and

the 7th rising edge of RXC past the falling edge of /HBEN for a

CAM read cycle. Read data is output to the D(15-0) bus

immediately prior to /HBRDY going LOW.

For both non-arbitrated Write and Read cycles, /HBRDY goes

HIGH after the first rising edge of RXC past the rising edge of

/WS or /RS in Intel mode or /UDS, /LDS in Motorola mode.

/HBEN and /HBDIR return HIGH and /HBRDY will go

three-state after the next rising edge of RXC.

On a FIFO write, /HBRDY goes LOW after the fifth rising edge

of RXC past the falling edge of /HBEN. On a FIFO read,

/HBRDY goes LOW after the fourth rising edge of RXC past the

falling edge of /HBEN.

MAC Interface

The TB block and/or the SRB notify the MAC interface to copy

or reject a frame through the XMATCH and the XFAIL pins for

the TMS380CX6, or the /FLUSH pin for the 82C581, using the

TEXAS bit in the Control register to select the operating mode.

When Routine 2 is enabled, the results from the TB and the

SRB are combined.

Transceiver Interface

The MU9C8148 connects to the received data bus between the

TMS38053/4 and the TMS380CX6. The differential Manchester

encoded data received from the Token Ring transceiver is input

to the RXD pin which clocked by the RXC clock. The /RDY

signal indicates the presence of received data on the RXD pin.

The Transceiver interface notifies the TB block and the SRB

that it has detected a JK Start delimiter in the incoming data

stream and to begin parsing the other fields of the frame. The

Transceiver interface performs a number of error checks:

whether the data contained any control characters before an

ED was received; that no second SD is received before an ED

is received; and, /RDY is still asserted. In any of these cases,

both the TB and SRB are notified and reception of data is

cancelled. Also checked are: the correctness of the FCS, the

value of the E bit in the ED, and the values of both C bits and

both A bits in the FS field. If there is an error situation detected

in one of these items, the TB is notified not to start Routine 1.

Host Processor Interface

The Host Processor interface is configured for Intel or Motorola

addressing modes using the /INTEL pin. In both modes the

MU9C8148 is a slave on the processor bus and can be

programmed using the registers described in this document.

The MU9C8148 provides /HBEN and /HBDIR to enable the

user to add external bi-directional buffers in the D15-D0

datalines. In Intel mode, ALE is used to latch the address lines.

In Motorola mode, both /UDS and /LDS are used to load the

upper and lower bytes to all of the registers including the

Instruction buffer and FIFO.

Two MU9C8148s Sharing One LANCAM

Two MU9C8148s may share the same LANCAM string if they

are operating at the same frequency, using /RQ and /RQI to

arbitrate the LANCAM access by setting the ASSRQ bit in the

Control register to HIGH. One MU9C8148 is set to be Master,

and given Routines 0–2, and the other is set to be Slave and

given the non-time-critical Routines 3–6 in addition to Routines

0–2. Routines 3–6 running on the Slave can be interrupted

immediately by time-critical routines running on either the

Master or Slave, but if both MU9C8148s try to run a high

priority routine at the same time, the Master device will be

given priority, and the Slave device will start its routine after the

Master has finished.

INSTRUCTION SET DESCRIPTION

Instruction:

LANCAM Instruction

Binary Op Code: iiii iiii iiii iiii wce0

i Instruction Code (see The LANCAM Handbook)

w The state of /W

c The state of /CM

e The state of /EC

This instruction transfers data or commands to or from the

LANCAM. Instructions from the LANCAM instruction set are

described in the LANCAM Handbook. The state of the control

outputs /W, /CM and /EC at the falling edge of /E for this cycle

are defined by w,c, and e.

Instruction:

Stop Execution

Binary Op Code: 0000 0000 0000 0000 xxx1

x Don't Care

The “Stop Execution” instruction stops the execution of the

routine currently running. Control is transferred to the arbiter.

Instruction:

Wait for match for yyyyB + 4 cycles, if no

match then execute at Branch Routine

Address selected.

Binary Op Code: 0001 yyyy rrrr rrrr xxx1

y Wait period

r Reserved (set LOW)

x Don't Care

This instruction waits for a maximum period of yyyyB + 4 clock

cycles for the /MI input to become active, asserting XMATCH

and XFAIL as appropriate. If no match condition occurs during

that period, a branch is executed to the address stored in the

Branch Routine address determined by the frame type. If a

match condition is detected, execution proceeds to the

instruction at the next address.

Rev. 5.5 Draft web

8

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