Logic Symbol
Connection Diagram
Pin Descriptions
Pin Names
Description
HD
High Drive Enable Input (Active HIGH)
DIR
Direction Control Input
A1–A8
B1–B8
A9–A13
Y9–Y13
A14–A17
C14–C17
PLHIN
PLH
Inputs or Outputs
Inputs or Outputs
Inputs
Outputs
Outputs
Inputs
Peripheral Logic HIGH Input
Peripheral Logic HIGH Output
HLHIN
HLH
Host Logic HIGH Input
Host Logic HIGH Output
Truth Table
Inputs
Outputs
DIR HD
L
L B1–B8 Data to A1–A8, and
A9–A13 Data to Y9–Y13 (Note 1)
C14–C17 Data to A14–A17
PLH Open Drain Mode
L
H B1–B8 Data to A1–A8, and
A9–A13 Data to Y9–Y13
C14–C17 Data to A14–A17
H
L A1–A8 Data to B1–B8 (Note 2)
A9–A13 Data to Y9–Y13 (Note 1)
C14–C17 Data to A14–A17
PLH Open Drain Mode
H
H A1–A8 Data to B1–B8
A9–A13 Data to Y9–Y13
C14–C17 Data to A14–A17
Note 1: Y9–Y13 Open Drain Outputs with 1.4 kΩ pullups
Note 2: B1–B8 Open Drain Outputs with 1.4 kΩ pullups
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