CL-PS7110 View Datasheet(PDF) - Cirrus Logic

Part Name

Description

Manufacturer

CL-PS7110

Low-Power System-on-a-Chip

Cirrus Logic 

CL-PS7110

Low-Power System-on-a-Chip

LIST OF TABLES

Table 1-1.

Table 1-2.

Table 1-3.

Table 2-1.

Table 2-2.

Table 3-1.

Table 3-2.

Table 3-3.

Table 3-4.

Table 3-5.

Table 3-6.

Table 3-7.

Table 3-8.

Table 3-9.

Table 3-10.

Table 3-11.

Table 3-12.

Table 3-13.

Table 3-14.

Table 3-15.

Table 3-16.

Table 3-17.

Table 4-1.

Table 4-2.

Table 4-3.

Table 4-4.

Table 4-5.

Table 4-6.

Table 4-7.

Table 4-8.

Interrupt Allocation..................................................................................................14

Physical-to-DRAM Address Mapping......................................................................19

DRAM Address Mapping ........................................................................................20

External Signal Functions .......................................................................................32

Numeric Pin Listing .................................................................................................35

Memory Map...........................................................................................................39

Internal I/O Memory Locations................................................................................40

Bits in SYSCON ......................................................................................................43

Keyboard Scan Field...............................................................................................43

ADCCLK Frequencies.............................................................................................45

Bits in the System Status Flags Register................................................................45

Values of the Bus Width Field .................................................................................48

PCMCIA Mode Bus Width.......................................................................................48

Values of the Random Access Wait State Field......................................................49

Values of the Sequential Access Wait State Field ..................................................49

Sense of DC-to-DC Converter Control Lines ..........................................................54

Internal UART Bit Rates..........................................................................................56

UART Word Length .................................................................................................56

Least-Significant Word Palette Assignments .........................................................57

Most-Significant Word Palette Assignments ...........................................................57

Grayscale Value to Color Mapping..........................................................................57

Bits in SYNCIO Write Register................................................................................58

DC Characteristics ..................................................................................................61

AC Characteristics ..................................................................................................62

I/O Buffer Output Characteristics ............................................................................70

CL-PS7110 Hardware Test Modes..........................................................................70

EPB Test Mode Signal Assignment.........................................................................71

Oscillator and PLL Test Mode Signals ....................................................................72

Chip Select Address Ranges During Test ROM Mode............................................73

Expansion and ROM Interface Bus Width During Test ROM Mode ........................73

May 1997

DATA BOOK v1.5

7

LIST OF TABLES

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