VNQ6040STR-E View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

VNQ6040STR-E

Quad channel high-side driver

STMicroelectronics 

Functional description

2

Functional description

VNQ6040S-E

2.1

Operating modes

The device can operate in 7 different modes:

• Reset mode

Reset mode is entered after startup, and if the digital voltage VDD falls below VDDR. In

this condition, the outputs are controlled by the direct inputs INX. The SPI is inactive, all

SPI registers are cleared.

• Fail Safe mode

After reset, after wake-up from Standby or Sleep mode 1 or 2 and in case of several

error conditions, the device operates in Fail Safe mode. In this condition, the outputs

are controlled by the direct inputs INX regardless of SPI commands. Diagnosis is

available through SPI bus.

• Normal mode

If the device is in Fail Safe mode, Normal mode can be entered using a special SPI

sequence. In Normal mode, outputs can be driven by SPI commands or a combination

of SPI command and direct inputs INX. Diagnosis is available through SPI bus and

CurrentSense pin.

• Standby mode

If the device is in Normal mode or Fail Safe mode, Standby mode can be entered using

a special SPI sequence. In Standby mode the consumption of the digital part is nearly

0. The outputs are controlled by the direct inputs INX regardless of SPI commands.

• Sleep mode 1

If the device is in Reset mode and the direct inputs INX are all 0, the device enters

Sleep mode 1. In Sleep mode 1, the output stages are off, the current consumption of

the digital part is nearly 0 and the current consumption on VCC is below ISoff.

• Sleep mode 2

If the device is in Standby mode and the direct inputs INX are all 0, the device enters

Sleep mode 2. In Sleep mode 2, the output stages are off, the current consumption of

the digital part is nearly 0 and the current consumption on VCC is below ISoff.

• Battery undervoltage mode

If the battery voltage VCC is below the undervoltage threshold, the device enters Battery

undervoltage mode. In this condition, the output stages are off regardless of SPI

commands.

The Reset mode, the Fail Safe mode and the Sleep mode 1 are combined into the Limp

home mode. In this mode the chip is able to operate without the connection to the SPI. All

transitions between the states in limp home mode are driven by VDD and INX. The outputs

are controlled by the direct inputs INX.

For an overview over the operating modes and the triggering conditions please refer to

Table 2.

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DocID18061 Rev 11

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