MPC5200CVR400B(2006) View Datasheet(PDF) - Freescale Semiconductor

Part Name

Description

Manufacturer

MPC5200CVR400B
(Rev.:2006)

SDRAM/DDR Memory Controller

Freescale Semiconductor 

Electrical and Thermal Characteristics

NOTE

Beware of changing the values on the pins of the reset configuration word

after the deassertion of PORRESET. This may cause problems because it

may change the internal clock ratios and so extend the PLL locking process.

3.3.4 External Interrupts

The MPC5200B provides three different kinds of external interrupts:

• Four IRQ interrupts

• Eight GPIO interrupts with simple interrupt capability (not available in power-down mode)

• Eight WakeUp interrupts (special GPIO pins)

The propagation of these three kinds of interrupts to the core is shown in the following graphic:

IRQ0

8 GPIOs

8 GPIOs

IRQ1

IRQ2

IRQ3

8

GPIO Std

8 GPIO WakeUp

cint

Encoder

int

Grouper

Encoder

CORE_CINT

CORE_INT

e300 Core

PIs

Main Interrupt

Controller

Notes:

1. PIs = Programmable Inputs

2. Grouper and Encoder functions imply programmability in software

Figure 4. External Interrupt Scheme

Due to synchronization, prioritization, and mapping of external interrupt sources, the propagation of

external interrupts to the core processor is delayed by several IP_CLK clock cycles. The following table

specifies the interrupt latencies in IP_CLK cycles. The IP_CLK frequency is programmable in the Clock

Distribution Module (see Note Table 16).

Table 16. External Interrupt Latencies

Interrupt Type

Interrupt Requests

Pin Name

IRQ0

IRQ0

IRQ1

IRQ2

IRQ3

Clock Cycles

10

10

10

10

10

Reference Clock

IP_CLK

IP_CLK

IP_CLK

IP_CLK

IP_CLK

Core Interrupt

critical (cint)

normal (int)

normal (int)

normal (int)

normal (int)

SpecID

A4.1

A4.2

A4.3

A4.4

A4.5

MPC5200B Data Sheet, Rev. 1

18

Freescale Semiconductor

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