SPC5200CBV400BR2 View Datasheet(PDF) - Freescale Semiconductor
Part Name
Description
Manufacturer
SPC5200CBV400BR2 Datasheet PDF : 72 Pages
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IRQ0
8 GPIOs
8 GPIOs
IRQ1
8
GPIO Std
8 GPIO WakeUp
cint
Encoder
int
Grouper
Encoder
CORE_CINT
CORE_INT
e300 Core
IRQ2
IRQ3
PIs
Main Interrupt
Controller
Notes:
1. PIs = Programmable Inputs
2. Grouper and Encoder functions imply programmability in software
Figure 4. External Interrupt Scheme
Due to synchronization, prioritization, and mapping of external interrupt sources, the propagation of external interrupts to the
core processor is delayed by several IP_CLK clock cycles. The following table specifies the interrupt latencies in IP_CLK
cycles. The IP_CLK frequency is programmable in the Clock Distribution Module (see Table 16).
Table 16. External Interrupt Latencies
Interrupt Type
Pin Name
Clock Cycles Reference Clock Core Interrupt SpecID
Interrupt Requests
IRQ0
10
IP_CLK
critical (cint)
A4.1
IRQ0
10
IP_CLK
normal (int)
A4.2
IRQ1
10
IP_CLK
normal (int)
A4.3
IRQ2
10
IP_CLK
normal (int)
A4.4
IRQ3
10
IP_CLK
normal (int)
A4.5
Standard GPIO Interrupts GPIO_PSC3_4
12
IP_CLK
normal (int)
A4.6
GPIO_PSC3_5
12
IP_CLK
normal (int)
A4.7
GPIO_PSC3_8
12
IP_CLK
normal (int)
A4.8
GPIO_USB_9
12
IP_CLK
normal (int)
A4.9
GPIO_ETHI_4
12
IP_CLK
normal (int)
A4.10
GPIO_ETHI_5
12
IP_CLK
normal (int)
A4.11
GPIO_ETHI_6
12
IP_CLK
normal (int)
A4.12
GPIO_ETHI_7
12
IP_CLK
normal (int)
A4.13
GPIO WakeUp Interrupts GPIO_PSC1_4
12
IP_CLK
normal (int)
A4.15
GPIO_PSC2_4
12
IP_CLK
normal (int)
A4.16
GPIO_PSC3_9
12
IP_CLK
normal (int)
A4.17
GPIO_ETHI_8
12
IP_CLK
normal (int)
A4.18
GPIO_IRDA_0
12
IP_CLK
normal (int)
A4.19
DGP_IN0
12
IP_CLK
normal (int)
A4.20
DGP_IN1
12
IP_CLK
normal (int)
A4.21
NOTES:
1) The frequency of IP_CLK depends on register settings in Clock Distribution Module. See the MPC5200B User’s Manual.
MPC5200B Data Sheet, Rev. 4
16
Freescale Semiconductor
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