MAX14821ETG(2011) View Datasheet(PDF) - Maxim Integrated
Part Name
Description
Manufacturer
MAX14821ETG Datasheet PDF : 31 Pages
| |||
MAX14821
IO-Link Device Transceiver
Pin/Bump Configurations
TOP VIEW
18 17 16 15 14 13
DI 19
12 TXC
GND 20
11 TXQ
C/Q 21
DO 22
MAX14821
10 I.C.
9 VL
VCC 23
+
VP 24
*EP
8 SDI
7 SDO
1234 56
TQFN
*CONNECT EXPOSED PAD TO GND.
TOP VIEW
(BUMP SIDE DOWN)
MAX14821
1
2
3
4
5
+
A
VCC
LDOIN
V5
LDO33
SCLK
B
C/Q
VP
IRQ
CS
SDO
C
GND
GND
I.C.
SDI
VL
D
DO
UV
WU
TXC
TXQ
E
DI
LI
LO
RX
TXEN
WLP
Pin/Bump Descriptions
PIN
TQFN-EP WLP
1
A2
2
A3
3
A4
4
B3
5
A5
6
B4
7
B5
8
C4
9
C5
10
C3
NAME
FUNCTION
LDOIN
V5
LDO33
IRQ
SCLK
CS
SDO
SDI
VL
I.C.
5V Linear Regulator Input. Bypass LDOIN to GND with a 0.1FF ceramic capacitor.
5V Power-Supply Input and 5V Linear Regulator Output. Bypass V5 to GND with a 0.1FF
ceramic capacitor for 10mA load capability. Add the recommended compensation network
to increase the source capability to 30mA. See the 5V and 3.3V Linear Regulators section for
more information.
3.3V Linear Regulator Output. Bypass LDO33 to GND with a 1FF ceramic capacitor.
Active-Low Interrupt Request Output. IRQ is a push-pull output referenced to VL.
SPI Clock Input
Active-Low SPI Chip-Select Input
SPI Serial-Data Output
SPI Serial-Data Input
Logic-Level Supply Input. VL defines the logic levels on all the logic inputs and outputs.
Bypass VL to GND with a 0.1FF ceramic capacitor.
Internally Connected. Connect to VL or leave unconnected.
���������������������������������������������������������������� Maxim Integrated Products 14
Share Link: 