MAX2121 View Datasheet(PDF) - Maxim Integrated
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MAX2121 Datasheet PDF : 18 Pages
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Complete Direct-Conversion L-Band Tuner
START
WRITE DEVICE ADDRESS
1100000
R/W ACK READ FROM STATUS BYTE-1 REGISTER ACK
1
—
—
—
READ FROM STATUS BYTE-2 REGISTER
—
ACK/
NACK
—
STOP
Figure 3. Example: Receive Data from Read Registers
Read Cycle
When addressed with a read command, the MAX2121
allows the master to read back a single register, or mul-
tiple successive registers.
A read cycle begins with the bus master issuing a
START condition followed by the seven slave address
bits and a write bit (R/W = 0). The MAX2121 issues an
ACK if the slave address byte is successfully received.
The bus master must then send the address of the first
register it wishes to read (see Table 1 for register
addresses). The slave acknowledges the address.
Then, a START condition is issued by the master, fol-
lowed by the seven slave address bits and a read bit
(R/W = 1). The MAX2121 issues an ACK if the slave
address byte is successfully received. The MAX2121
starts sending data MSB first with each SCL clock
cycle. At the 9th clock cycle, the master can issue an
ACK and continue to read successive registers, or the
master can terminate the transmission by issuing a
NACK. The read cycle does not terminate until the mas-
ter issues a STOP condition.
Figure 3 illustrates an example in which registers 0, 1,
and 2 are read back.
Application Information
The MAX2121 downconverts RF signals in the 925MHz
to 2175MHz range directly to the baseband I/Q signals.
RF Input
The RF input of the MAX2121 is internally matched to
75Ω. Only a DC-blocking capacitor is needed. See the
Typical Application Circuit.
RF Gain Control
The MAX2121 features a variable-gain low-noise ampli-
fier providing 73dB of RF gain range. The voltage con-
trol (VGC) range is 0.5V (minimum attenuation) to 2.7V
(maximum attenuation).
Baseband Variable-Gain Amplifier
The receiver baseband variable-gain amplifiers provide
15dB of gain control range programmable in 1dB
steps. The VGA gain can be serially programmed
through the I2C interface by setting bits BBG[3:0] in the
Control register.
Table 16. Maximum Crystal ESR
Requirement
ESRMAX ()
80
60
XTAL FREQUENCY (MHz)
12 < fXTAL 14
14 < fXTAL 30
Baseband Lowpass Filter
The MAX2121 includes an on-chip 5th-order Butterworth
filter with 1st-order group delay compensation.
DC Offset Cancellation
The DC offset cancellation is required to maintain the
I/Q output dynamic range. Connecting an external
capacitor between IDC+ and IDC- forms a highpass fil-
ter for the I channel and an external capacitor between
QDC+ and QDC- forms a highpass filter for the Q chan-
nel. Keep the value of the external capacitor less than
47nF to form a typical highpass corner of 250Hz.
XTAL Oscillator
The MAX2121 contains an internal reference oscillator,
reference output divider, and output buffer. All that is
required is to connect a crystal through a series 1nF
capacitor. To minimize parasitics, place the crystal and
series capacitor as close as possible to pin 14 (XTAL).
See Table 16 for crystal (XTAL) ESR (equivalent series
resistance) requirements.
Programming the Fractional
N- Synthesizer
The MAX2121 utilizes a fractional-N type synthesizer for
LO frequency programming. To program the frequency
synthesizer, the N and F values are encoded as
straight binary numbers. Determination of these values
is illustrated by the following example:
fLO is 2170MHz
fXTAL is 27 MHz
Phase-detector comparison frequency is from 12MHz
and 30MHz
R divider = R[4:0] = 1
fCOMP = 27MHz/1 = 27MHz
D = fLO/fCOMP = 2170/27 = 80.37470
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