XRT83VSH316 View Datasheet(PDF) - Exar Corporation

Part Name

Description

Manufacturer

XRT83VSH316

IC LIU SH T1/E1/J1 16CH 316STBGA

Exar Corporation 

XRT83VSH316

16-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT

1.0 PIN DESCRIPTIONS

REV. 1.0.2

MICROPROCESSOR

NAME

PIN

CS

A19

ALE_TS

D15

WR_R/W

E15

RD_WE

C18

RDY_TA

R5

INT

B19

PCLK

U6

ADDR9

ADDR8

ADDR7

ADDR6

ADDR5

ADDR4

ADDR3

ADDR2

ADDR1

ADDR0

E17

D17

Y18

W18

W17

V17

V16

U16

U15

T15

TYPE

I

I

I

I

O

O

I

I

DESCRIPTION

Chip Select Input

Active low signal. This signal enables the microprocessor interface by pulling

chip select "Low". The microprocessor interface is disabled when the chip

select signal returns "High". This pin is used for both the Parallel or the Serial

Interface modes.

NOTE: Internally pulled "High" with a 50k  resistor.

Address Latch Enable Input (Transfer Start)

See the Microprocessor section of this datasheet for a description.

NOTE: Internally pulled "Low" with a 50k  resistor.

Write Strobe Input (Read/Write)

See the Microprocessor section of this datasheet for a description.

NOTE: Internally pulled "Low" with a 50k  resistor.

Read Strobe Input (Write Enable)

See the Microprocessor section of this datasheet for a description.

NOTE: Internally pulled "Low" with a 50k  resistor.

Ready Output (Transfer Acknowledge)

See the Microprocessor section of this datasheet for a description.

Interrupt Output

Active low signal. This signal is asserted "Low" when a change in alarm status

occurs. Once the status registers have been read, the interrupt pin will return

"High". GIE (Global Interrupt Enable) must be set "High" in the appropriate

global register to enable interrupt generation.

NOTE: This pin is an open-drain output that requires an external 10K pull-up

resistor.

Micro Processor Clock Input

In a synchronous microprocessor interface, PCLK is used as the internal timing

reference for programming the LIU.

NOTE: Internally pulled "Low" with a 50k  resistor.

Address Bus Input

ADDR[9:0] are a direct address bus for permitting access to the internal regis-

ters.

NOTE: Internally pulled "Low" with a 50k  resistor.

3

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