TMC5062 View Datasheet(PDF) - Unspecified
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TMC5062 Datasheet PDF : 92 Pages
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TMC5062 DATASHEET (Rev. 1.10 / 2016-APR-28)
10
Pin
Number Type Function
VCC
33
DIE_PAD
-
GND
5V supply input for digital circuitry within chip and charge pump.
Attach 470nF capacitor to GND (GND plane). May be supplied by
5VOUT. A 2.2Ω resistor is recommended for decoupling noise from
5VOUT. When using an external supply, make sure, that VCC comes
up before or in parallel to 5VOUT.
Connect the exposed die pad to a GND plane. Provide as many as
possible vias for heat transfer to GND plane.
Table 2.1 Low voltage digital and analog power supply pins
Pin
Number Type
CPO
35
O(VCC)
CPI
36
I(VCP)
VCP
37
Table 2.2 Charge pump pins
Function
Charge pump driver output. Outputs 5V (GND to VCC) square wave
with 1/16 of internal oscillator frequency.
Charge pump capacitor input: Provide external 22 nF / 50 V capacitor
to CPO.
Output of charge pump. Provide external 100 nF capacitor to VS.
Pin
Number Type Function
ENC1A/INT 1
I/O
ENC1B/PP
2
I/O
CSN/IO0
3
I/O
SCK/IO1
4
I/O
SDI/IO2
5
I/O
SDO/IO3
8
I/O
SWIOP
9
I/O
SWION
10
I/O
CLK
11
I
SWSEL
12
I
REFR2
25
I
REFL2
26
I
REFR1
27
I
REFL1
28
I
DRV_ENN
29
I
TST_MODE
-
48
I
13, 23, 38 N.C.
Input A for incremental encoder 1. Can be programmed to provide
interrupt output based on ramp generator flags RAMP_STAT bits 4, 5,
6 & 7 and encoder null event status ENC_STATUS bit 0
(poscmp_enable=1).
Input B for incremental encoder 1. Can be programmed to provide
position compare output for motor 1 (poscmp_enable=1).
Chip select input of SPI interface, programmable IO in UART mode
Serial clock input of SPI interface, programmable IO in UART mode
Data input of SPI interface, programmable IO in UART mode
Data output of SPI interface (Tristate, enabled with CSN=0),
programmable IO in UART mode
Single wire UART interface I/O. Has internal 100K pulldown resistor.
Multi-purpose input in SPI mode.
Single wire I/O (negative) for differential mode. Leave open in non-
differential mode when operating at 5V IO voltage or tie to desired
threshold voltage. Serial output in ring mode. Multi-purpose input in
SPI mode or encoder 2 N input.
Clock input. Tie to GND using short wire for internal clock or supply
external clock. The first high signal disables the internal oscillator
until power down.
Interface selection input. Tie to GND for SPI mode, tie to VCC_IO for
single wire (UART) interface mode.
Right reference switch input for motor 2
Left reference switch input for motor 2
Right reference switch input for motor 1
Left reference switch input for motor 1
Enable input for motor drivers. The power stage becomes switched
off (all motor outputs floating) when this pin becomes driven to a
high level. Tie to GND for normal operation.
Test mode input. Tie to GND using short wire.
Unused pins – no internal electrical connection. Leave open or tie to
GND for compatibility with future devices.
Table 2.3 Digital I/O pins (all related to VCC_IO supply)
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