K4B4G1646B View Datasheet(PDF) - Samsung
Part Name
Description
Manufacturer
K4B4G1646B Datasheet PDF : 64 Pages
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K4B4G1646B
datasheet
Rev. 1.0
DDR3 SDRAM
1. Ordering Information
[ Table 1 ] Samsung 4Gb DDR3 B-die ordering information table
Organization DDR3-1066 (7-7-7) DDR3-1333 (9-9-9)6 DDR3-1600 (11-11-11)5 DDR3-1866 (13-13-13)4 DDR3-2133 (14-14-14)3 Package
256Mx16 K4B4G1646B-HCF8 K4B4G1646B-HCH9 K4B4G1646B-HCK0 K4B4G1646B-HCMA K4B4G1646B-HCNB 96 FBGA
256Mx16
-
K4B4G1646B-HIH9 K4B4G1646B-HIK0
-
-
96 FBGA
256Mx16
-
K4B4G1646B-HPH9 K4B4G1646B-HPK0
-
-
NOTE :
1. Speed bin is in order of CL-tRCD-tRP.
2. 13th digit stands for below.
"C" : Comercial temp/Normal power
"I" : Industrial temp/Normal power
"P" : Industrial temp/Low power(IDD6 only)
3. DDR3-2133(14-14-14) is backward compatible to DDR3-1866(13-13-13), DDR3-1600(11-11-11), DDR3-1333(9-9-9), DDR3-1066(7-7-7)
4. DDR3-1866(13-13-13) is backward compatible to DDR3-1600(11-11-11), DDR3-1333(9-9-9), DDR3-1066(7-7-7)
5. DDR3-1600(11-11-11) is backward compatible to DDR3-1333(9-9-9), DDR3-1066(7-7-7)
6. DDR3-1333(9-9-9) is backward compatible to DDR3-1066(7-7-7)
96 FBGA
2. Key Features
[ Table 2 ] 4Gb DDR3 B-die Speed bins
Speed
DDR3-800
DDR3-1066
DDR3-1333
DDR3-1600
DDR3-1866
DDR3-2133
Unit
6-6-6
7-7-7
9-9-9
11-11-11
13-13-13
14-14-14
tCK(min)
2.5
1.875
1.5
1.25
1.07
0.935
ns
CAS Latency
6
7
9
11
13
14
nCK
tRCD(min)
15
13.125
13.5
13.75
13.91
13.09
ns
tRP(min)
15
13.125
13.5
13.75
13.91
13.09
ns
tRAS(min)
37.5
37.5
36
35
34
33
ns
tRC(min)
52.5
50.625
49.5
48.75
47.91
46.09
ns
• JEDEC standard 1.5V(1.425V~1.575V)
• VDDQ = 1.5V(1.425V~1.575V)
• 400 MHz fCK for 800Mb/sec/pin, 533MHz fCK for 1066Mb/sec/pin,
667MHz fCK for 1333Mb/sec/pin, 800MHz fCK for 1600Mb/sec/pin,
933MHz fCK for 1866Mb/sec/pin, 1066 MHz fCK for 2133Mb/sec/pin
• 8 Banks
• Programmable CAS Latency(posted CAS): 5,6,7,8,9,10,11,12,13,14
• Programmable Additive Latency: 0, CL-2 or CL-1 clock
• Programmable CAS Write Latency (CWL) = 5 (DDR3-800), 6
(DDR3-1066), 7 (DDR3-1333) , 8 (DDR3-1600), 9 (DDR3-1866) and
10 (DDR3-2133)
• 8-bit pre-fetch
• Burst Length: 8 (Interleave without any limit, sequential with starting
address “000” only), 4 with tCCD = 4 which does not allow seamless
read or write [either On the fly using A12 or MRS]
• Bi-directional Differential Data-Strobe
The 4Gb DDR3 SDRAM B-die is organized as a 32Mbit x 16 I/Os x 8banks,
device. This synchronous device achieves high speed double-data-rate
transfer rates of up to 2133Mb/sec/pin (DDR3-2133) for general applica-
tions.
The chip is designed to comply with the following key DDR3 SDRAM fea-
tures such as posted CAS, Programmable CWL, Internal (Self) Calibration,
On Die Termination using ODT pin and Asynchronous Reset .
All of the control and address inputs are synchronized with a pair of exter-
nally supplied differential clocks. Inputs are latched at the crosspoint of dif-
ferential clocks (CK rising and CK falling). All I/Os are synchronized with a
pair of bidirectional strobes (DQS and DQS) in a source synchronous fash-
ion. The address bus is used to convey row, column, and bank address
information in a RAS/CAS multiplexing style. The DDR3 device operates
with a single 1.5V(1.425V~1.575V) power supply and
1.5V(1.425V~1.575V).
The 4Gb DDR3 B-die device is available in 96ball FBGAs(x16).
• Internal(self) calibration : Internal self calibration through ZQ pin
(RZQ : 240 ohm ± 1%)
• On Die Termination using ODT pin
• Average Refresh Period 7.8us at lower than TCASE 85°C, 3.9us at
85°C < TCASE < 95 °C
• Support Industrial Temp ( -40 ∼ 85°C )
• Asynchronous Reset
• Package : 96 balls FBGA - x16
• All of Lead-Free products are compliant for RoHS
• All of products are Halogen-free
NOTE : 1. This data sheet is an abstract of full DDR3 specification and does not cover the common features which are described in “DDR3 SDRAM Device Operation & Timing
Diagram”.
2. The functionality described and the timing specifications included in this data sheet are for the DLL Enabled mode of operation.
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