MT6162N View Datasheet(PDF) - MediaTek Inc
Part Name
Description
Manufacturer
MT6162N Datasheet PDF : 32 Pages
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MT6162
Table 4 Pin Allocation / Function Description
Pin Name
Description
Pin Name
Description
A2 REFCLK1
Reference Clock Buffer #1 main for
digital baseband
K1 VDD_18
Regulated supply for IC
A4 REFCLK3
A6 NC
Reference Clock Buffer #3
No connect
K17 TX_LB1
L2 VSUP1
Tx Low band Driver #1
Internal Supply (ext. cap)
A8 XO1/REFIN Crystal Pin #1 or Ref Clock Input
A10 CLK_MODE Select DCXO or VCTCXO
L18 GND
M1 RX_BBQN
Ground; connect to GND plane on
PCB
Rx Baseband Output – Q Channel
A12 GND
A14 GND
A16 GND
B1 GND
B3 REFCLK2
B5 VDDXO
Ground; connect to GND plane on
PCB
M17 VSUP3
Internal Supply (ext. cap)
Konka_WCX Ground; connect to GND plane on
PCB
Ground; connect to GND plane on
PCB
Ground; connect to GND plane on
PCB
Reference Clock Buffer #2
N2 RX_BBQP
N18 VDD_28a
P1 RX_BBIN
P17 NC
Rx Baseband Output – Q Channel
Regulated supply for IC
Rx Baseband Output – I Channel
No connect
Regulated supply for VCXO/DCXO
R2 RX_BBIP
Rx Baseband Output – I Channel
B7 XO2
Crystal Pin #2
R18 NC
No connect
B9 VTUNE
B11 VSUP2b
B13 PDET
AFCDAC Output
Internal Supply (ext. cap)
Power Detector Input
T1 GND
T17 NC
U2 LNA1N
Ground; connect to GND plane on
PCB
No Connect
Rx Path #1 Input
B15 GND
Ground; connect to GND plane on
PCB
U4 LNA2N
Rx Path #2 Input
B17 TX_IN
Tx Baseband Input – I Channel
U6 LNA3N
Rx Path #3 Input
C2 EN
Serial Interface Enable (BSI)
U8 LNA4N
Rx Path #4 Input
C18 TX_IP
D1 VINT
D17 TX_QN
Tx Baseband Input – I Channel
Serial interface control logic
Tx Baseband Input – Q Channel
U10 LNA5N
U12 LNA6N
U14 LNA7N
Rx Path #5 Input
Rx Path #6 Input
Rx Path #7 Input
E2 DATA1
Serial Data I/O (BSI)
U16 LNA8P
Rx Path #8 Input
E18 TX_QP
Tx Baseband Input –Q Channel
U18 GND
Ground; connect to GND plane on
PCB
F11 DATA0
F17 TX_HB3
G2 CLK
Serial Data I/O (BSI)
Tx High band Driver #3
Serial Interface Clock (BSI)
V3 LNA1P
V5 LNA2P
V7 LNA3P
Rx Path #1 Input
Rx Path #2 Input
Rx Path #3 Input
G18 TX_HB2
Tx High band Driver #2
V9 LNA4P
Rx Path #4 Input
H1 VDD_28b Regulated supply for IC
V11 LNA5P
Rx Path #5 Input
Konka_WCX H17 TX_HB1
J2 VSUP2a
J18 TX_LB2
Tx High band Driver #1 (2G only)
Internal Supply (ext. cap)
Tx Low band Driver #2 (2G only)
notes
1.
2.
VSUP2a and VSUP2b should be shorted on the PCB
VDD_28a and VDD_28b should be shorted on the PCB
V13 LNA6P
V15 LNA7P
V17 LNA8N
Rx Path #6 Input
Rx Path #7 Input
Rx Path #8 Input
3. Pin T17 is recommended a ‘No Connect’ pin to balance parasitics on the RF Input pins
4. CLK_MODE:
GND = Internal DCXO (Crystal mode)
Floating or connect to VDDXO = External Clock (VCTCXO)
REV. (1.5) Mar 20th 2011
- 9 - MediaTek Proprietary & Confidential Information
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