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NTE1853 View Datasheet(PDF) - NTE Electronics

Part Name
Description
Manufacturer
NTE1853 Datasheet PDF : 6 Pages
1 2 3 4 5 6
Timing Characteristics (Contd):
Parameter
SDAB (Note 9)
Subcode Data Setup Time
Subcode Data Hold Time
Input Rise Time
Input Fall Time
Outputs
WSBD (Note 6 & Note 10)
Word Select Setup Time
Word Select Hold Time
WSBD (Note 6)
Output Rise Time
Output Fall Time
DABD (Note 6 & Note 10)
Data Setup Time
Data Hold Time
Outputs (Contd)
DABD (Note 6)
Output Rise Time
Output Fall Time
CLBD (Note 6 & Note 10)
Clock Period
Clock Low Time
Clock High Time
Clock Setup Time
Clock Hold Time
CLBD (Note 6)
Output Rise Time
Output Fall Time
DABD (Note 6 & Note 11)
Data Setup Time
Data Hold Time
Symbol Test Conditions Min
Typ
Max Unit
tSU, tSDAT
tHD, tSDAT
tR
tF
40
ns
0
ns
20
ns
20
ns
tSU, tWS
tHD, tWS
tR
tF
tSU, tDATD
tHD, tDATD
40
0
ns
ns
20
ns
20
ns
40
0
ns
ns
tR
tF
tCK
tCKL
tCKH
tSU, tCLD
tHD, tCLD
tR
tF
tSU, tDATBD
tHD, tDATBD
20
ns
20
ns
161
177
197 ns
65
ns
65
ns
40
ns
0
ns
20
ns
20
ns
40
60
ns
ns
Note 6. Reference levels = 0.8V and 2.0V
Note 7. The signal CLAB can run at either 2.8MHz (1/4 system clock) or 1.4MHz (1/8 system clock)
under typical conditions. It does not have a minimum or maximum frequency, but is limited
to being 1/4 or 1/8 of the system clock frequency.
Note 8. Input setup and hold times measured with respect to clock input from Achip (CLAB). Refer-
ence levels = 0.8V and 2.0V.
Note 9. Input setup and hold times measured with respect to subcode burst clock input from Achip
(SCAB). Reference levels = 0.8V and 2.0V.
Note10. Output setup and hold times measured with respect to system clock output (XSYS).
Note 11. Output setup and hold times measured with respect to clock output (CLBD).

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