IS42R16320D View Datasheet(PDF) - Integrated Silicon Solution
Part Name
Description
Manufacturer
IS42R16320D Datasheet PDF : 66 Pages
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IS42/45R86400D/16320D/32160D, IS42/45S86400D/16320D/32160D
PIN FUNCTIONS
Symbol Type
A0-A12
Input Pin
BA0, BA1
CAS
CKE
Input Pin
Input Pin
Input Pin
CLK
Input Pin
CS
Input Pin
DQM: x8
DQML, DQMH: x16
DQM0-DQM3: x32
Input Pin
DQ0-DQ7: x8
Input/Output
DQ0-DQ15: x16
DQ0-DQ31: x32
RAS
Input Pin
WE
Input Pin
Vddq
Vdd
Vssq
Vss
Power Supply Pin
Power Supply Pin
Power Supply Pin
Power Supply Pin
Function (In Detail)
Address Inputs: A0-A12 are sampled during the ACTIVE command (row-address
A0-A12) and READ/WRITE command (column address A0-A9, A11 (x8); A0-A9
(x16); A0-A8 (x32); with A10 defining auto precharge) to select one location out of
the memory array in the respective bank. A10 is sampled during a PRECHARGE
command to determine if all banks are to be precharged (A10 HIGH) or bank
selected by BA0, BA1 (LOW). The address inputs also provide the op-code during a
LOAD MODE REGISTER command.
Bank Select Address: BA0 and BA1 defines which bank the ACTIVE, READ, WRITE
or PRECHARGE command is being applied.
CAS, in conjunction with the RAS and WE, forms the device command. See the
"Command Truth Table" for details on device commands.
The CKE input determines whether the CLK input is enabled. The next rising edge
of the CLK signal will be valid when is CKE HIGH and invalid when LOW. When CKE
is LOW, the device will be in either power-down mode, clock suspend mode, or self
refresh mode. CKE is an asynchronous input.
CLK is the master clock input for this device. Except for CKE, all inputs to this device
are acquired in synchronization with the rising edge of this pin.
The CS input determines whether command input is enabled within the device.
Command input is enabled when CS is LOW, and disabled with CS is HIGH. The
device remains in the previous state when CS is HIGH.
DQx pins control the bytes of the I/O buffers. For example with x16, in read mode,
DQML and DQMH control the output buffer. When DQML or DQMH is LOW, the
corresponding buffer byte is enabled, and when HIGH, disabled. The outputs go to
the HIGH impedance state when DQML/DQMH is HIGH. This function corresponds
to OE in conventional DRAMs. In write mode, DQML and DQMH control the input
buffer. When DQML or DQMH is LOW, the corresponding buffer byte is enabled,
and data can be written to the device. When DQML or DQMH is HIGH, input data is
masked and cannot be written to the device.
Data on the Data Bus is latched on DQ pins during Write commands, and buffered for
output after Read commands.
RAS, in conjunction with CAS and WE, forms the device command. See the "Com-
mand Truth Table" item for details on device commands.
WE, in conjunction with RAS and CAS, forms the device command. See the "Com-
mand Truth Table" item for details on device commands.
Vddq is the output buffer power supply.
Vdd is the device internal power supply.
Vssq is the output buffer ground.
Vss is the device internal ground.
Integrated Silicon Solution, Inc. — www.issi.com
7
Rev. A
08/29/2012
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