CY8C21345-24SXIT View Datasheet(PDF) - Cypress Semiconductor
Part Name
Description
Manufacturer
CY8C21345-24SXIT Datasheet PDF : 39 Pages
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CY8C21345
CY8C22345
CY8C22545
Pinouts
This PSoC device family is available in a variety of packages that are listed in the following tables. Every port pin (labeled with a “P”)
is capable of Digital I/O. However, Vss, Vdd, and XRES are not capable of Digital I/O.
CY8C22345, CY8C21345 28-pin SOIC
Table 2. Pin Definitions
Type
Pin No.
Pin Name
Digital Analog
Description
1
I/O I, MR P0[7] Integration Capacitor for MR
2
I/O I, ML P0[5] Integration Capacitor for ML
3
I/O I, ML P0[3]
4
I/O I, ML P0[1]
5
I/O I, ML P2[7] To Compare Column 0
6
I/O
ML
P2[5] Optional ADC External Vref
7
I/O
ML
P2[3]
8
I/O
ML
P2[1]
9
Power
Vss Ground Connection
10
I/O
ML
P1[7] I2C serial clock (SCL)
11
I/O
ML
P1[5] I2C serial data (SDA)
12
I/O
ML
P1[3]
13
I/O
ML
P1[1] I2C serial clock (SCL),
ISSP-SCLK[4]
14
Power
Vss Ground Connection
15
I/O
MR
P1[0] I2C serial Clock (SCL),
ISSP-SDATA[4]
16
I/O
MR
P1[2]
17
I/O
MR
P1[4] Optional external clock input
(EXT-CLK)
18
I/O
MR
P1[6]
19
Input
XRES Active High Pin Reset with
Internal Pull Down
20
I/O
MR
P2[0]
21
I/O
MR
P2[2]
22
I/O
MR
P2[4]
23
I/O I, MR P2[6] To Compare Column 1
24
I/O I, MR P0[0]
25
I/O I, MR P0[2]
26
I/O I, MR P0[4]
27
I/O I, MR P0[6]
28
Power
Vdd Supply Voltage
Figure 3. Pin Diagram
AI, MR, P0[7] 1
AI, ML, P0[5] 2
AI, ML, P0[3] 3
AI, ML, P0[1] 4
AI, ML, P2[7] 5
ADC_Ext_Vref, ML, P2[5] 6
ML, P2[3] 7
ML, P2[1] 8
Vss 9
I2C SCL, ML, P1[7] 10
I2C SDA, ML, P1[5] 11
ML, P1[3] 12
I2C SCL, ML, P1[1] 13
Vss 14
28
27
26
25
24
23
SOIC 22
21
20
19
18
17
16
15
Vdd
P0[6], MR, AI
P0[4], MR, AI
P0[2], MR, AI
P0[0], MR, AI
P2[6], MR, AI
P2[4], MR
P2[2], MR
P2[0], MR
XRES
P1[6], MR
P1[4], MR, EXTCLK
P1[2], MR
P1[0], MR, I2C SDATA
LEGEND: A = Analog, I = Input, O = Output, M=Analog Mux input, MR= Analog Mux right input, ML= Analog Mux left input.
Note
4. ISSP pin which is not HI-Z at POR.
Document Number: 001-43084 Rev. *Q
Page 8 of 39
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