CYM74SP55-60 View Datasheet(PDF) - Cypress Semiconductor
Part Name
Description
Manufacturer
CYM74SP55-60 Datasheet PDF : 7 Pages
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PRELIMINARY
CYM74BP54
CYM74P54/55
CYM74SP54/55
Pin Definitions
Common Signals
Description
VCC
GND
5V Supply
Ground
A7–A19
A3–0, A4–0
A3–1, A4–1
Addresses from processor
Lower address from chipset, identical to the bank1 addresses
Lower address from chipset, identical to the bank0 addresses, A3-1, A4-1 not used on
CYM74P54
A5–0, A6–0
Lower address from processor (CYM74P5X, CYM74SP5X- identical to the bank1
addresses)
CE0, CE1
OE0, OE1
WE0, WE1,WE2,WE3
WE4,WE5,WE6,WE7
PD0–PD2
D0–D63
NC
Chip Enable (same signal), CE1 not used on CYM74P54
Output Enable (same signal), OE1 not used on CYM74P54
Byte Write Enables
Presence Detect pins
Data lines from processor
Signal not connected on module.
CYM74BP54 Only Signals
Description
CALE
Latch Enable
CYM74P5X, CYM74SP5X Signals
Description
VCCQ
DP0–DP7
ADSP0, ADSP1
3.3V Supply
Data Parity lines (Optional)
Processor Address Strobe, ADSP1 not used on CYM74P54
ADSC0,ADSC1
Cache Controller Address Strobe, ADSC1 not used on CYM74P54
ADV0, ADV1
Burst Address Advance, ADV1 not used on CYM74P54
A5–1, A6–1
Lower address from processor, identical to the bank0 addresses, A5-1, A6-1 not used on
CYM74P54
CLK0, CLK1, CLK2, CLK3
Clock signals (each should be given own clk driver); CLK0 used on CYM74P5X,
CYM74SP5X; CLK1 not used on CYM74P54; CLK2 and CLK3 are RSVD
Presence Detect Pins
Asynchronous – CYM74BP54
Synchronous Pipelined – CYM74P54
Synchronous Pipelined – CYM74P55
Synchronous Burst – CYM74SP54
Synchronous Burst – CYM74SP55
PD2
NC
TBD
TBD
GND
GND
PD1
GND
TBD
TBD
GND
GND
PD0
NC
TBD
TBD
NC
GND
5
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