T8301 View Datasheet(PDF) - Agere -> LSI Corporation

Part Name

Description

Manufacturer

T8301

Internet Protocol Telephone Phone-On-A-Chip™ IP Solution DSP

Agere -> LSI Corporation 

Advance Data Sheet

December 2000

T8301 Internet Protocol Telephone

Phone-On-A-Chip IP Solution DSP

5 Audio Input/Output Circuitry

The discussions in this section pertain to circuitry that is outside of the dotted outline in Figure 3 on page 8.

5.1 Analog Audio Input Channels

The T8301 contains analog interfaces designed to support a 150 Ω handset as well as an additional microphone

and two speakers.

The T8301 integrated circuit contains two audio analog inputs. There is a single-ended input (AINAN) to be con-

nected to a standard business telephone handset receiver. There is a differential input (AINCP, AINCN) to be con-

nected to a microphone. This provides the T8301 with the input circuitry to implement a speakerphone. The

differential input is directly connected to a 30 dB amplifier. The input select multiplexer routes AINAN or the output

of the fixed 30 dB amplifier to a programmable gain amplifier (PGA). The programmable gain amplifier is adjustable

from 0 dB to 21 dB in 3 dB steps. The signal output from the programmable gain amplifier is then routed to the

audio codec block to be digitized.

Each of the input signals AINAN, AINCP, and AINCN are ac-coupled to their T8301 inputs by a 0.2 µF capacitor.

The maximum signal input to the codec is 2.5 Vp-p. If the user sets the amplification to a value that would produce

a larger signal than 2.5 Vp-p, the audio codec will saturate and clip the input waveform.

The maximum input signal from the handset or from the microphone that can be supported for each gain setting is

listed in Table 7. Since the microphone amplifier has a maximum specified signal of 40 mV, the maximum micro-

phone input is not supported for PGA settings of 0 dB and 3 dB.

5.2 Programmable Gain Amplifier (PGA)

The programmable gain amplifier is using the PGAS[2:0] bits of the aioc_reg (see Table 11 on page 21). The set-

table gain values and their tolerances are shown below as well as the maximum allowed input signal voltage from

each of the input signals. Inputs greater than these values will saturate the input codec and produce clipped wave-

forms.

Table 7. Programmable Gain Amplifier Maximum

Bit Code

Gain

000

0 dB ± 0.5 dB

001

3 dB ± 0.5 dB

010

6 dB ± 0.5 dB

011

9 dB ± 0.5 dB

100

12 dB ± 0.5 dB

101

15 dB ± 1.0 dB

110

18 dB ± 1.0 dB

111

21 dB ± 1.5 dB

AINAN

2.500 Vp-p

1.770 Vp-p

1.250 Vp-p

0.844 Vp-p

0.625 Vp-p

0.442 Vp-p

0.313 Vp-p

0.221 Vp-p

Max Input Signal

AINCN, AINCP

Not supported

Not supported

40.0 mVp-p

28.3 mVp-p

20.0 mVp-p

14.2 mVp-p

10.0 mVp-p

7.1 mVp-p

Lucent Technologies Inc.

17

Share Link: