MC145425P View Datasheet(PDF) - Motorola => Freescale

Part Name

Description

Manufacturer

MC145425P

ISDN Universal Digital Loop Transceivers II

Motorola => Freescale 

In the master, time–out begins on the rising edge of the

third MSI following the last received burst. This is equivalent

to two MSI frames. The VD output is forced low during time–

out. The B channel output data will be unknown, but the

D channel bits will remain at their last values. Successful de-

modulation of a burst from the slave will result in leaving the

time–out state on the next rising MSI edge.

When the PD pin is used as an output on the slave UDLT,

time–out controls the pin. Time–out forces the PD output low

to indicate that the device has powered itself down. In this

case, the slave will not transmit to the master. However,

when a valid burst is received, time–out ends and the PD pin

is driven high to indicate power up. This feature allows the

slave UDLT to self–power–up and down in demand–powered

loop systems.

NOTE

The slave uses a free running clock during time–

out. After a long period without a burst from the

master, the timing between master and slave

could be such that more than one burst will be

needed to resync the two devices.

MSI

VD

DCLK

D1I, D2I

D1O, D2O

TDC/RDC

TE1

TE2

RE1

RE2

Tx

Rx

125 µs

1ST BIT

1ST BIT

2ND BIT

2ND BIT

B CHANNEL 1 OUTPUT

DON’T CARE

HIGH–Z

B CHANNEL 2 OUTPUT

B CHANNEL 1 INPUT

B CHANNEL 2 INPUT

Figure 1. Typical MC145421 Master ISDN UDLT Timing

MOTOROLA

MC145421•MC145425

9

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